JPS5986333A - クロツクパルス発生回路 - Google Patents

クロツクパルス発生回路

Info

Publication number
JPS5986333A
JPS5986333A JP57196417A JP19641782A JPS5986333A JP S5986333 A JPS5986333 A JP S5986333A JP 57196417 A JP57196417 A JP 57196417A JP 19641782 A JP19641782 A JP 19641782A JP S5986333 A JPS5986333 A JP S5986333A
Authority
JP
Japan
Prior art keywords
circuit
pulse
clock pulse
response
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57196417A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0331016B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Hiroshi Tokumatsu
得松　博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP57196417A priority Critical patent/JPS5986333A/ja
Publication of JPS5986333A publication Critical patent/JPS5986333A/ja
Publication of JPH0331016B2 publication Critical patent/JPH0331016B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/191—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using at least two different signals from the frequency divider or the counter for determining the time difference

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP57196417A 1982-11-08 1982-11-08 クロツクパルス発生回路 Granted JPS5986333A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57196417A JPS5986333A (ja) 1982-11-08 1982-11-08 クロツクパルス発生回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57196417A JPS5986333A (ja) 1982-11-08 1982-11-08 クロツクパルス発生回路

Publications (2)

Publication Number Publication Date
JPS5986333A true JPS5986333A (ja) 1984-05-18
JPH0331016B2 JPH0331016B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-05-02

Family

ID=16357503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57196417A Granted JPS5986333A (ja) 1982-11-08 1982-11-08 クロツクパルス発生回路

Country Status (1)

Country Link
JP (1) JPS5986333A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5894240A (ja) * 1981-11-30 1983-06-04 Nec Home Electronics Ltd クロツクパルス発生回路

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5894240A (ja) * 1981-11-30 1983-06-04 Nec Home Electronics Ltd クロツクパルス発生回路

Also Published As

Publication number Publication date
JPH0331016B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-05-02

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