JPS5983053U - 集積回路 - Google Patents

集積回路

Info

Publication number
JPS5983053U
JPS5983053U JP17850482U JP17850482U JPS5983053U JP S5983053 U JPS5983053 U JP S5983053U JP 17850482 U JP17850482 U JP 17850482U JP 17850482 U JP17850482 U JP 17850482U JP S5983053 U JPS5983053 U JP S5983053U
Authority
JP
Japan
Prior art keywords
integrated circuit
amplifier
terminal
semiconductor integrated
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17850482U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0438529Y2 (enrdf_load_stackoverflow
Inventor
松村　鋭一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17850482U priority Critical patent/JPS5983053U/ja
Publication of JPS5983053U publication Critical patent/JPS5983053U/ja
Application granted granted Critical
Publication of JPH0438529Y2 publication Critical patent/JPH0438529Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Amplifiers (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP17850482U 1982-11-26 1982-11-26 集積回路 Granted JPS5983053U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17850482U JPS5983053U (ja) 1982-11-26 1982-11-26 集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17850482U JPS5983053U (ja) 1982-11-26 1982-11-26 集積回路

Publications (2)

Publication Number Publication Date
JPS5983053U true JPS5983053U (ja) 1984-06-05
JPH0438529Y2 JPH0438529Y2 (enrdf_load_stackoverflow) 1992-09-09

Family

ID=30387532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17850482U Granted JPS5983053U (ja) 1982-11-26 1982-11-26 集積回路

Country Status (1)

Country Link
JP (1) JPS5983053U (enrdf_load_stackoverflow)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5649556A (en) * 1979-09-28 1981-05-06 Toshiba Corp Mos integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5649556A (en) * 1979-09-28 1981-05-06 Toshiba Corp Mos integrated circuit

Also Published As

Publication number Publication date
JPH0438529Y2 (enrdf_load_stackoverflow) 1992-09-09

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