JPS5649556A - Mos integrated circuit - Google Patents

Mos integrated circuit

Info

Publication number
JPS5649556A
JPS5649556A JP12500079A JP12500079A JPS5649556A JP S5649556 A JPS5649556 A JP S5649556A JP 12500079 A JP12500079 A JP 12500079A JP 12500079 A JP12500079 A JP 12500079A JP S5649556 A JPS5649556 A JP S5649556A
Authority
JP
Japan
Prior art keywords
substrate
pad
self
bias circuit
back bias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12500079A
Other languages
Japanese (ja)
Inventor
Hideo Noguchi
Tsuginari Iwamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12500079A priority Critical patent/JPS5649556A/en
Publication of JPS5649556A publication Critical patent/JPS5649556A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
    • H01L27/0222—Charge pumping, substrate bias generation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To normalize the operation of a self-back bias circuit with substrate potential stabilized by letting induced charge go to a power source through a large capacity formed between the underside of a junction pad as input and output terminals and a substrate and connected to the source. CONSTITUTION:When a plurality of N-channel gates are formed on a P type Si substrate 1, a field oxide film 2 under the site range of a junction pad to be provided is selectively removed, a thermal oxidation film 3 and a poly-Si conductive film 4 somewhat larger than an Al pad 6 are stacked, and the film 4 is grounded. Next, SiO25 is stacked by CVD method and an Al pad 6 to be connected to input or output circuits is formed, and covered with a PSG 7. Further a self-back bias circuit is provided in addition to an N-channel gate. Thereby, the charge induced between the substrate and a capacity part due to the charge pump effect can be effectively let go to a power source upon operation, the single-source power supply and speed- up to a high level of the self-back bias circuit become possible and an MOSIC can be obtaind for normal circuit operation.
JP12500079A 1979-09-28 1979-09-28 Mos integrated circuit Pending JPS5649556A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12500079A JPS5649556A (en) 1979-09-28 1979-09-28 Mos integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12500079A JPS5649556A (en) 1979-09-28 1979-09-28 Mos integrated circuit

Publications (1)

Publication Number Publication Date
JPS5649556A true JPS5649556A (en) 1981-05-06

Family

ID=14899395

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12500079A Pending JPS5649556A (en) 1979-09-28 1979-09-28 Mos integrated circuit

Country Status (1)

Country Link
JP (1) JPS5649556A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5983053U (en) * 1982-11-26 1984-06-05 日本電気株式会社 integrated circuit
JPS6073258U (en) * 1983-10-25 1985-05-23 日本電気株式会社 integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5983053U (en) * 1982-11-26 1984-06-05 日本電気株式会社 integrated circuit
JPH0438529Y2 (en) * 1982-11-26 1992-09-09
JPS6073258U (en) * 1983-10-25 1985-05-23 日本電気株式会社 integrated circuit

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