JPS6073258U - integrated circuit - Google Patents
integrated circuitInfo
- Publication number
- JPS6073258U JPS6073258U JP1983164952U JP16495283U JPS6073258U JP S6073258 U JPS6073258 U JP S6073258U JP 1983164952 U JP1983164952 U JP 1983164952U JP 16495283 U JP16495283 U JP 16495283U JP S6073258 U JPS6073258 U JP S6073258U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- voltage supply
- bonding pad
- active elements
- supply bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は、直流増幅回路の一例を示す回路図、第2図は
従来のG、 A、集積回路におけるICチップと、DC
ブロック用キャパシタとの構成を示した図、第3図は本
考案の集積回路の構成例を示す図、第4図は第3図のA
−A’における断面図である。
図において、101・・・・・・入力端、102・・・
・・・出力端、103・・・・・・ゲート電圧供給端子
、104・・・・・・ドレイン電圧供給端子、105,
106・・・・・・DCブdツク用主キヤパシタ107
・・・・・・ゲート電圧供給用抵抗、108・・・・・
・負荷抵抗、109・・・・・・G1As電界効果トラ
ンジスタ、201・・・・・・G、 A、−IC基板、
202,203・・・・・・MISキャパシタ、204
・・・・・・ボンディングワイヤ、303゜405・・
・・・・電圧供給用ポンディングパッド、310.41
0・・・・・・グランドパターン、400・・・・・・
半絶縁性G。A、高抵抗基板、420・・・・・・誘電
体層、をそれぞれ示す。Fig. 1 is a circuit diagram showing an example of a DC amplifier circuit, and Fig. 2 shows an IC chip in a conventional G, A, integrated circuit, and a DC amplifier circuit.
FIG. 3 is a diagram showing a configuration example of the integrated circuit of the present invention, and FIG. 4 is a diagram showing the configuration with a block capacitor.
It is a sectional view at -A'. In the figure, 101... input terminal, 102...
...Output end, 103...Gate voltage supply terminal, 104...Drain voltage supply terminal, 105,
106... Main capacitor for DC book 107
...Resistance for gate voltage supply, 108...
・Load resistance, 109...G1As field effect transistor, 201...G, A, -IC board,
202, 203... MIS capacitor, 204
...Bonding wire, 303°405...
...Ponding pad for voltage supply, 310.41
0...Ground pattern, 400...
Semi-insulating G. A, a high-resistance substrate, and 420 . . . dielectric layer are shown, respectively.
Claims (1)
を行なう信号線を形成して回路を構成する集積回路にお
いて、電圧供給用ポンディングパッドの下部に誘電体層
を挾んでグラヴド層を配置する事により前記電圧供給用
ポンディングパッド自体をキャパシタとして形成するこ
とを特徴とする集積回路。In an integrated circuit where a circuit is constructed by forming a plurality of active elements on a substrate and signal lines connecting the active elements, a gloved layer is formed by sandwiching a dielectric layer under a voltage supply bonding pad. An integrated circuit characterized in that the voltage supply bonding pad itself is formed as a capacitor by arranging it.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983164952U JPS6073258U (en) | 1983-10-25 | 1983-10-25 | integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983164952U JPS6073258U (en) | 1983-10-25 | 1983-10-25 | integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6073258U true JPS6073258U (en) | 1985-05-23 |
Family
ID=30361505
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1983164952U Pending JPS6073258U (en) | 1983-10-25 | 1983-10-25 | integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6073258U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4911587A (en) * | 1972-06-01 | 1974-02-01 | ||
JPS5649556A (en) * | 1979-09-28 | 1981-05-06 | Toshiba Corp | Mos integrated circuit |
-
1983
- 1983-10-25 JP JP1983164952U patent/JPS6073258U/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4911587A (en) * | 1972-06-01 | 1974-02-01 | ||
JPS5649556A (en) * | 1979-09-28 | 1981-05-06 | Toshiba Corp | Mos integrated circuit |
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