JPS5999469U - Wiring pattern for electronic circuits - Google Patents

Wiring pattern for electronic circuits

Info

Publication number
JPS5999469U
JPS5999469U JP20008382U JP20008382U JPS5999469U JP S5999469 U JPS5999469 U JP S5999469U JP 20008382 U JP20008382 U JP 20008382U JP 20008382 U JP20008382 U JP 20008382U JP S5999469 U JPS5999469 U JP S5999469U
Authority
JP
Japan
Prior art keywords
wiring pattern
electronic circuits
electronic circuit
electrodes
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20008382U
Other languages
Japanese (ja)
Inventor
井原 哲茂
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP20008382U priority Critical patent/JPS5999469U/en
Publication of JPS5999469U publication Critical patent/JPS5999469U/en
Pending legal-status Critical Current

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  • Bipolar Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は集積回路内の電子回路の一部、第2図は従来の
配線パタニン、第3図は集積回路素子内のnpn型トラ
ンジスタの一例、第4図は本考案−実施例である。図に
おいて、TRI、TR2はトランジスタ、R1は抵抗で
ある。
FIG. 1 shows a part of an electronic circuit in an integrated circuit, FIG. 2 shows a conventional wiring pattern, FIG. 3 shows an example of an NPN transistor in an integrated circuit element, and FIG. 4 shows an embodiment of the present invention. In the figure, TRI and TR2 are transistors, and R1 is a resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電子回路素子間の電極を接続する電子回路用配線パター
ンにおいて、複数電極を有する電子回路素子の各電極に
接続される位置の配線パターン端部の形状を、同一素子
の電極間ではそれぞれ異るよう構成した電子回路用配線
パターン。
In a wiring pattern for an electronic circuit that connects electrodes between electronic circuit elements, the shape of the end of the wiring pattern at the position connected to each electrode of an electronic circuit element having multiple electrodes is made to be different between electrodes of the same element. The constructed wiring pattern for the electronic circuit.
JP20008382U 1982-12-23 1982-12-23 Wiring pattern for electronic circuits Pending JPS5999469U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20008382U JPS5999469U (en) 1982-12-23 1982-12-23 Wiring pattern for electronic circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20008382U JPS5999469U (en) 1982-12-23 1982-12-23 Wiring pattern for electronic circuits

Publications (1)

Publication Number Publication Date
JPS5999469U true JPS5999469U (en) 1984-07-05

Family

ID=30425613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20008382U Pending JPS5999469U (en) 1982-12-23 1982-12-23 Wiring pattern for electronic circuits

Country Status (1)

Country Link
JP (1) JPS5999469U (en)

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