JPS5974639A - 薄板状集積回路基板の製法 - Google Patents

薄板状集積回路基板の製法

Info

Publication number
JPS5974639A
JPS5974639A JP57184566A JP18456682A JPS5974639A JP S5974639 A JPS5974639 A JP S5974639A JP 57184566 A JP57184566 A JP 57184566A JP 18456682 A JP18456682 A JP 18456682A JP S5974639 A JPS5974639 A JP S5974639A
Authority
JP
Japan
Prior art keywords
chip
integrated circuit
substrate
card
circuit chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57184566A
Other languages
English (en)
Other versions
JPH0557119B2 (ja
Inventor
Kenzo Masuda
増田　健三
Kenichi Ishibashi
謙一 石橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57184566A priority Critical patent/JPS5974639A/ja
Publication of JPS5974639A publication Critical patent/JPS5974639A/ja
Publication of JPH0557119B2 publication Critical patent/JPH0557119B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01052—Tellurium [Te]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Credit Cards Or The Like (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は集積回路チップに加わる曲げ応力を低減できる
薄板状集積回路基板に関する。
近年、集積回路（ＩＣ）や大規模集積回路（ＬＳＩ）を
内蔵したカード類、たとえばキャッジ−カード、クレジ
ットカード、ＩＤカード、電子ロック、コンピータやＰ
Ｏ８端末等の補助記憶カード等の使用上の便利さが注目
され、実用化への要求が高まっている。
ところで、このようなカー上類においては、その取扱中
や携帯中等にカードに対して相当大きな曲げ応力がかか
ることがあるが、カードの厚さが薄いので、曲げにより
集積回路チップが破壊されてしまうという問題がある。
この問題は、カードの薄板化の傾向につれて、ますます
大きくなυつつある。
本発明の目的は、前記した問題点に鑑み、集積回路チッ
プにかかる曲げ応力を低減し、チップの破壊を防止する
ことのできる薄板状集積回路基板を提供することにある
。
以下、本発明を図面に示す一実施例にしたがって詳細に
説明する。
第１図は本発明による薄板状集積回路基板の一実施例に
おける集積回路チップのカード基板への取付方向を示す
平面図である。
この実施例において、カード基板１はたとえばガラス−
エポキシ材料よシなる薄板状構造であシ、キャッシュカ
ード、クレジットカード、ＩＤカード、電子ロック、コ
ンピュータやＰＯ８端末の補助記憶カード等の基板とし
て用いられる。
このカード基板１は中央部に集積回路チップ内蔵用の凹
部２を有し、その全体的平面形状は長方形であり、長手
方向の寸法−ｇ＋＞短手方向の寸法１２となっているの
で、このカード基板１に対する曲げ応力は長手方向の方
が短手方向よりも大きくなる。
前記凹部２内には、集積回路チップ３が取υ付けられる
が、この集積回路チップ３の平面形状は短手方向が寸法
ｐ３　、長手方向が寸法−１３４（ｐ　ｓ〈１４　）の
長方形である。
この集積回路チップ３の取付方向は、その短手方向がカ
ード基板１の曲げ応力の大きい方向すなわち本実施例で
は該カード基板１の長手方向となっている。
この集積回路チップ３はカード基板１の凹部２内に取υ
付けた後、第２図に示すように、該集積回路チップ３の
ボンディングバンドと凹部２内に形成した導電層との間
にワイヤ４をボンディングして電気的に接続し、配線５
を介してカード基板１の上面のプリント配線６から外部
への電気的導通を行なう。
また、前記凹部２の中には、封止用のレジン７がボッテ
ィング等で供給され、集積回路チップ３およびワイヤ４
を凹部２内に封止している。
本実施例においては、前記の如く、集積回路チップ３は
その短手方向がカード基板１の曲げ応力の大きい方向（
長手方向）となるよう配置されているので、カード基板
１が長手方向に曲げられても、集積回路チップ３に加わ
る曲げ応力は低減され、該集積回路チップ３はその曲げ
応力に十分耐えることができ、チップ３の破壊を起こす
ことを防止できる。
したがって、カード基板１自体に要求される剛性は緩和
され、該カード基板１自体の厚さをよシ薄くし、さらに
使い易いものにすることができる。
また、本実施例では、カード基板１は短手方向には曲が
シにくいので、短手方向に大きい曲げ応力を受けず、集
積回路チップ３が長手方向に大きく曲げられて破壊され
ることもない。
なお、本発明は前記実施例に限定されるものではない。
たとえば、前記実施例では、カード基板１は長方形状と
して説明したが、正方形でもよく、その場合でも、カー
ド基板１の曲がシ易い方向に集積回路チップ３の短手方
向を配向すれば、同様に曲げ応力の低減、ひいては葉桜
回路チップ３の破壊防止を図ることができる。
以上説明したように、本発明によれば、集積回路チップ
に加わる曲げ応力を低減し、集積回路チップの破壊を防
止することができる。
【図面の簡単な説明】
第１図は本発明におけるカード基板に対する集積回路チ
ップの取付方向を示す概略的平面図、第２図は本発明に
よる薄板状集積回路基板の一実施例を示す断面図である
。 １・・・カード基板、２・・・凹部、３・・・集積回路
チップ、４・・・ワイヤ、５・・・配線、６・・・プリ
ント配線、７・・・封止用のレジン。 第　　１　　図

Claims (1)

    【特許請求の範囲】
  1. １、集積回路チップの短手方向が基板の曲げ応力の大き
    い方向となるよう集積回路チップを基板に取シ付けてな
    る薄板状集積回路基板。
JP57184566A 1982-10-22 1982-10-22 薄板状集積回路基板の製法 Granted JPS5974639A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57184566A JPS5974639A (ja) 1982-10-22 1982-10-22 薄板状集積回路基板の製法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57184566A JPS5974639A (ja) 1982-10-22 1982-10-22 薄板状集積回路基板の製法

Publications (2)

Publication Number Publication Date
JPS5974639A true JPS5974639A (ja) 1984-04-27
JPH0557119B2 JPH0557119B2 (ja) 1993-08-23

Family

ID=16155445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57184566A Granted JPS5974639A (ja) 1982-10-22 1982-10-22 薄板状集積回路基板の製法

Country Status (1)

Country Link
JP (1) JPS5974639A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62185072U (ja) * 1986-05-15 1987-11-25
JPH0199892A (ja) * 1987-10-13 1989-04-18 Dainippon Printing Co Ltd Ｉｃカードおよびｉｃカード用ｉｃモジュール
JPH0789281A (ja) * 1993-11-29 1995-04-04 Ryoden Kasei Co Ltd Ｉｃカード

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5329260A (en) * 1976-08-31 1978-03-18 Ishikawajima Harima Heavy Ind Device for penetrating plate of tension bridle
JPS5552698U (ja) * 1978-10-02 1980-04-08
JPS5752977A (en) * 1980-08-07 1982-03-29 Gao Ges Automation Org Identifying card and method of producing same
JPS58125892A (ja) * 1981-12-24 1983-07-27 ゲ−ア−オ−・ゲゼルシヤフト・フユ−ル・アウトマチオン・ウント・オルガニザチオン・エム・ベ−・ハ− 集積回路モジユ−ルを有する識別カ−ドおよびキヤリヤ要素

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5329260A (en) * 1976-08-31 1978-03-18 Ishikawajima Harima Heavy Ind Device for penetrating plate of tension bridle
JPS5552698U (ja) * 1978-10-02 1980-04-08
JPS5752977A (en) * 1980-08-07 1982-03-29 Gao Ges Automation Org Identifying card and method of producing same
JPS58125892A (ja) * 1981-12-24 1983-07-27 ゲ−ア−オ−・ゲゼルシヤフト・フユ−ル・アウトマチオン・ウント・オルガニザチオン・エム・ベ−・ハ− 集積回路モジユ−ルを有する識別カ−ドおよびキヤリヤ要素

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62185072U (ja) * 1986-05-15 1987-11-25
JPH0517269Y2 (ja) * 1986-05-15 1993-05-10
JPH0199892A (ja) * 1987-10-13 1989-04-18 Dainippon Printing Co Ltd Ｉｃカードおよびｉｃカード用ｉｃモジュール
JPH0789281A (ja) * 1993-11-29 1995-04-04 Ryoden Kasei Co Ltd Ｉｃカード

Also Published As

Publication number Publication date
JPH0557119B2 (ja) 1993-08-23

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