JPS5969826A - バツフア制御方式 - Google Patents

バツフア制御方式

Info

Publication number
JPS5969826A
JPS5969826A JP57179843A JP17984382A JPS5969826A JP S5969826 A JPS5969826 A JP S5969826A JP 57179843 A JP57179843 A JP 57179843A JP 17984382 A JP17984382 A JP 17984382A JP S5969826 A JPS5969826 A JP S5969826A
Authority
JP
Japan
Prior art keywords
unit
buffer
units
area
requested
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57179843A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6232518B2 (enExample
Inventor
Kenji Shioda
憲司 塩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57179843A priority Critical patent/JPS5969826A/ja
Priority to KR1019830004754A priority patent/KR880002099B1/ko
Publication of JPS5969826A publication Critical patent/JPS5969826A/ja
Priority to US07/016,519 priority patent/US4780815A/en
Publication of JPS6232518B2 publication Critical patent/JPS6232518B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System (AREA)
  • Information Transfer Systems (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Communication Control (AREA)
JP57179843A 1982-10-15 1982-10-15 バツフア制御方式 Granted JPS5969826A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP57179843A JPS5969826A (ja) 1982-10-15 1982-10-15 バツフア制御方式
KR1019830004754A KR880002099B1 (ko) 1982-10-15 1983-10-07 메모리의 제어방식
US07/016,519 US4780815A (en) 1982-10-15 1987-02-17 Memory control method and apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57179843A JPS5969826A (ja) 1982-10-15 1982-10-15 バツフア制御方式

Publications (2)

Publication Number Publication Date
JPS5969826A true JPS5969826A (ja) 1984-04-20
JPS6232518B2 JPS6232518B2 (enExample) 1987-07-15

Family

ID=16072866

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57179843A Granted JPS5969826A (ja) 1982-10-15 1982-10-15 バツフア制御方式

Country Status (3)

Country Link
US (1) US4780815A (enExample)
JP (1) JPS5969826A (enExample)
KR (1) KR880002099B1 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179662A (en) * 1989-08-31 1993-01-12 International Business Machines Corporation Optimized i/o buffers having the ability to increase or decrease in size to meet system requirements
JP3110035B2 (ja) * 1990-06-07 2000-11-20 株式会社東芝 携帯可能電子装置
JPH05233426A (ja) * 1992-02-20 1993-09-10 Fujitsu Ltd フラッシュ・メモリ使用方法
JP2957354B2 (ja) * 1992-05-13 1999-10-04 三菱電機株式会社 信号転送方法
GB2271202B (en) * 1992-10-01 1995-12-13 Digital Equipment Int Dynamic non-coherent cache memory resizing mechanism
US5916309A (en) * 1997-05-12 1999-06-29 Lexmark International Inc. System for dynamically determining the size and number of communication buffers based on communication parameters at the beginning of the reception of message
US6046817A (en) * 1997-05-12 2000-04-04 Lexmark International, Inc. Method and apparatus for dynamic buffering of input/output ports used for receiving and transmitting print data at a printer
US6031624A (en) * 1997-09-08 2000-02-29 Lexmark International, Inc. Method and apparatus for adaptive data buffering in a parallelized printing system
US6088777A (en) * 1997-11-12 2000-07-11 Ericsson Messaging Systems, Inc. Memory system and method for dynamically allocating a memory divided into plural classes with different block sizes to store variable length messages
US6615243B1 (en) * 1999-04-01 2003-09-02 Thomson Licensing S.A. System and method for programming and transmitting macros for controlling audio/video devices
KR20010027606A (ko) * 1999-09-14 2001-04-06 구자홍 디스크 기록매체의 데이터 전송장치 및 방법
US7809806B1 (en) 2001-08-02 2010-10-05 Cisco Technology, Inc. Neighbor discovery using address registration protocol over ELMI
US6681309B2 (en) * 2002-01-25 2004-01-20 Hewlett-Packard Development Company, L.P. Method and apparatus for measuring and optimizing spatial segmentation of electronic storage workloads
US6996676B2 (en) * 2002-11-14 2006-02-07 International Business Machines Corporation System and method for implementing an adaptive replacement cache policy
US20060275895A1 (en) * 2003-06-27 2006-12-07 Bio-Circuit Biogas producing facility with anaerobic hydrolysis
DK1794979T3 (en) 2004-09-10 2017-07-24 Cavium Inc Selective copying of data structure
US7594081B2 (en) 2004-09-10 2009-09-22 Cavium Networks, Inc. Direct access to low-latency memory
US7941585B2 (en) 2004-09-10 2011-05-10 Cavium Networks, Inc. Local scratchpad and data caching system
US9026302B2 (en) 2009-11-06 2015-05-05 Irobot Corporation Methods and systems for complete coverage of a surface by an autonomous robot

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4435752A (en) * 1973-11-07 1984-03-06 Texas Instruments Incorporated Allocation of rotating memory device storage locations
CH604322A5 (enExample) * 1975-02-10 1978-09-15 Siemens Ag
US4393501A (en) * 1981-02-26 1983-07-12 General Electric Company Line protocol for communication system
US4520453A (en) * 1982-11-01 1985-05-28 Ampex Corporation Address transformation system having an address shuffler

Also Published As

Publication number Publication date
JPS6232518B2 (enExample) 1987-07-15
KR840007286A (ko) 1984-12-06
US4780815A (en) 1988-10-25
KR880002099B1 (ko) 1988-10-15

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