JPS5945721A - Cmos論理回路 - Google Patents
Cmos論理回路Info
- Publication number
- JPS5945721A JPS5945721A JP57157009A JP15700982A JPS5945721A JP S5945721 A JPS5945721 A JP S5945721A JP 57157009 A JP57157009 A JP 57157009A JP 15700982 A JP15700982 A JP 15700982A JP S5945721 A JPS5945721 A JP S5945721A
- Authority
- JP
- Japan
- Prior art keywords
- logic
- circuit
- fet
- setting section
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
- H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
Landscapes
- Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57157009A JPS5945721A (ja) | 1982-09-09 | 1982-09-09 | Cmos論理回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57157009A JPS5945721A (ja) | 1982-09-09 | 1982-09-09 | Cmos論理回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5945721A true JPS5945721A (ja) | 1984-03-14 |
| JPH0434332B2 JPH0434332B2 (OSRAM) | 1992-06-05 |
Family
ID=15640180
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57157009A Granted JPS5945721A (ja) | 1982-09-09 | 1982-09-09 | Cmos論理回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5945721A (OSRAM) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4799109A (en) * | 1985-02-07 | 1989-01-17 | U.S. Philips Corp. | Charge coupled sensor arrangement |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5342456U (OSRAM) * | 1976-09-16 | 1978-04-12 |
-
1982
- 1982-09-09 JP JP57157009A patent/JPS5945721A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5342456U (OSRAM) * | 1976-09-16 | 1978-04-12 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4799109A (en) * | 1985-02-07 | 1989-01-17 | U.S. Philips Corp. | Charge coupled sensor arrangement |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0434332B2 (OSRAM) | 1992-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5633600A (en) | Output buffer circuit having a minimized output voltage propagation | |
| JPS6382122A (ja) | 論理回路 | |
| EP0059722B1 (en) | Clocked igfet logic circuit | |
| US4239991A (en) | Clock voltage generator for semiconductor memory | |
| US6459556B1 (en) | Input buffer | |
| US4239990A (en) | Clock voltage generator for semiconductor memory with reduced power dissipation | |
| US5159214A (en) | Bicmos logic circuit | |
| EP0068892A2 (en) | Inverter circuit | |
| US4016430A (en) | MIS logical circuit | |
| JPS5945721A (ja) | Cmos論理回路 | |
| JP3329621B2 (ja) | 二電源インタフェイス回路 | |
| JPH0245381B2 (OSRAM) | ||
| US4546276A (en) | Full output voltage driver circuit using bootstrap capacitor and controlled delay circuitry | |
| JP2690624B2 (ja) | バッファ回路 | |
| JP3022812B2 (ja) | 出力バッファ回路 | |
| US6278157B1 (en) | Method and apparatus for elimination of parasitic bipolar action in logic circuits including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements | |
| JP2001237686A (ja) | 半導体集積回路 | |
| KR100596748B1 (ko) | 다이내믹 시모스 로직 | |
| KR940000252Y1 (ko) | 씨모스 낸드게이트 | |
| JP3038813B2 (ja) | BiCMOSゲート回路 | |
| JPH07154240A (ja) | 半導体集積回路 | |
| JP2586196B2 (ja) | 出力回路 | |
| JPH0613866A (ja) | パワーオンリセット回路 | |
| JPH11154857A (ja) | 演算回路 | |
| JP2934265B2 (ja) | 相補型mos出力回路 |