JPS5945721A - Cmos logical circuit - Google Patents

Abstract

PURPOSE:To decrease the kinds of an input signal to a logical set section and to improve the operating speed, by obtaining a desired logical output in an output node depending on whether plural logical arithmetic input signals satisfy a desired logical establishing condition. CONSTITUTION:When the input signals A, B are both ''1'' or ''0'', the logical set section 20 is made conductive, nodes Z, X go to ground potnetial when a control signal -phi goes to 1, and an M1 is conductive. Thus, a node W goes to ground potential and an output signal F goes to ''1''. When the input signal A is at ''0'' and the B is at ''1'', an N1 is ponductive, an N2 is cut off, a P2 is conductive, and although the same voltage as that at the node X appears at the node Y, the P1 is cut off by selecting suitably the threshold voltage of the P1. Thus, the logical set section 20 is nonconductive and a voltage at the node W is kept to the VDD. When the A is at ''1'' and the B is at ''0'', the voltage at the node W is kept to the VDD according to the said operation. Thus, the logical equation F=AB+(-A)(-B) is obtained at an output signal F.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to Cuos-FgT (
The present invention relates to CMOS logic circuits using complementary insulated gate field effect transistors, and particularly to synchronous logic circuits.

[Technical symbol of the invention]

An example of this type of conventional Clv (OS logic circuit, for example, an AND/OR type decoder circuit is shown in FIG. 1. In other words,
Q+ to Q6 are the entertainment type TV (OS-FE
Of these, the transistor Ql-0.4 is of N-channel type and constitutes the logic setting section 10, and the remaining P-channel transistor Q6 for precharging and N-channel transistor Q5 for discharging. The synchronizing pulse 7 causes one of the two to be brought into the 'jiff' state. In addition, 11 to 13 are inverter circuits, VDD
is the operating power supply voltage, A*B+A is the logic operation input signal of the logic setting section 10, respectively.

In the above circuit, when the synchronizing pulse φ is at the "1" level, the output terminal of the inverter circuit 13 on the output side is
The output signal F, which is expressed by the logical formula +A100, is activated.

[Problems with background technology]

By the way, in the above logic circuit, since the logic setting section 10 is composed of a single-conductivity type MOS-FI'ET, an inversion-related (AIA)l (B. Stone) is required as an input signal. , ^, Two inverter circuits 11 on the input side to make 100.

12 is required as an accessory circuit. For this reason, the number of elements used increases, and the area occupied by the circuit pattern increases when a multilayer circuit is constructed. This is not a good idea since it becomes a major factor in increasing the cost of integrated circuits. Also,
There is a drawback that the operating speed is reduced due to the signal delay caused by the inverter circuits 11 and 12TL.

[Objective of the Invention J] The present invention has been developed in view of the above-mentioned circumstances, and it is possible to reduce the types of input signals to the logic setting section, thereby making it possible to omit the auxiliary circuit, improving the operating speed, and reducing the circuit pattern area. The present invention provides a CMOS ethical circuit that can reduce the size of the system and reduce costs.

[Summary of the invention]

That is, in the CMOS logic circuit of the present invention, the logic setting section is formed in a combination circuit of an enhancement type first conductivity type UOS-FgT and a depletion type second conductivity type MOS-FB'l'', and this 46iI An enhancement type first conductor M is connected between one end of the control setting part and the output node.
The feature is that an OS-FET is inserted and connected, and a quasi-voltage is applied to the gate of this MOS-FET.

As a result, the logic setting section is placed in a conductive state or a cutoff state depending on whether or not the plurality of logic operation input signals satisfy a desired logic establishment condition, and a desired logic output can be obtained at the output node. In this case, since there is no need to create an inverted signal of the logic operation input signal as an input signal to the logic setting section, an attached circuit is not required, and the operation speed is improved, the circuit pattern area is reduced, and the circuit cost is reduced. become capable.

[Examples of actual inventions]

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

In Figure 2, N+ 'lN2 11JI +
M2 is the enhancement type Nf channel l, (OS-
``FET + M B is an enhancement type P-channel MOS-FET, P, and P! are depletion type P-channel MOS-FETs. Here, the above transistors NI * N2 + p, l p.

form a logic setting section 20, for example, as shown in the figure, transistors N and N2 are connected in series, transistors P and P are directly connected, and these transistors (N, , N2) and (PI# P2) are connected in parallel, and input signal A is guided to each gate of transistors N2 and P2, and input signal B is guided to each gate of transistors N1 and Pl. Therefore, the transistor M has a quasi-voltage V R'It(yIl
! is connected, the source terminal is connected to one end side node XK of the logic setting section 20, and the drain terminal is connected to the output node WK. In fact, the transistor M3 has a drain terminal connected to the operating power supply (VDD voltage), a source terminal connected to the output node W, and a control signal (for example, a synchronizing pulse φ) applied to the gate.

Further, the transistor M2 has a drain terminal connected to the node ZK on the other end side of the logic setting section 20, a source terminal grounded, and a gate to which the control signal φ is applied.

2I is an output inverter circuit, the input end of which is connected to the output node WVC@.

In the above logic circuit, the transistor M sets the maximum value of voltage at node X of its source terminal 1u11 to VR-
This is intended to limit the voltage to below VTHMI (where VT field J+ is the threshold voltage of the transistor M). Further, the transistor Ms is used to precharge the output node W when the f+i' control signal V is at the "0" level. Further, the transistor M2 is used to discharge the node 2 when the nitrification control 1 signal j is at the 1 level.The input signals A, B, and lJb are normally controlled by the precharging transistor M3. shall change during precharge.

Next, the first example of the above logic circuit will be explained. input signal A,
When B are both +1" or both 60" level, the logic setting unit 20 is set to 47IO, and when the control m11 signal φ = "1" level, the glf FIE of node 2 and M1 guides.

However, VR-VTHMI>O. Therefore, at this time, the voltage at the output node "W" becomes the ground potential, and the output signal F of the inverter circuit 21 becomes "1 level."

On the other hand, input signal A is at 0'' level, input No. 14 B
is at the "1" level, in the logic setting section 20, the transistor N. is set to 4, the transistor N2 is cut off, the transistor P2 is set to 4, and the ground 111 point Y between transistors P1 and P2 is connected to the node or The same four pressures appear,
This [striking force VY is VY=VR-VTHMI. Here, VDD-VTHPI>VR-VT[(Ml
-=--------...- fll (where VTIPI is 1 of the transistor P, the voltage), the transistor P is cut off. Therefore, theory J8! When the projection unit 20 is non-conducting, the voltage at the output node W is VDD KW. It will be time. This voltage is held dynamically and decreases over time.

Contrary to the above, input signal A is at "1" level, human input signal B
When the voltage is at the 70'' level, the signal is dynamically changed to 1 level per 1 level of the output node W according to the above operation.

In other words, in the above-mentioned C tAO S logic circuit shown in FIG. Since F is at the 10'' level, the logical expression of the output signal F is expressed as F=AB+AB:B of A. Here, the ■ symbol represents exclusive OR. Therefore, the circuit shown in FIG. 2 can obtain the same logic result as the circuit shown in FIG. 1, but the number of input signals to the logic setting section 20 is reduced to two compared to the circuit shown in FIG. This eliminates the need for ancillary circuits (the two inverter circuits 11, 1, ? on the input side in Figure 1), so the circuit pattern area can be reduced, and costs can be reduced when integrating the circuit. is possible. Furthermore, since there is no signal delay caused by the attached circuit, the operating speed of the logic circuit is improved.

FIGS. 3 to 5 each show other embodiments of the present invention. FIG. 3 shows the circuit in FIG. 2 further simplified and the number of elements reduced. Compared to FIG. 2, the transistor M2 is omitted, the node Z is grounded, and the reference voltage VR is applied to the gate of the transistor M. Mark the control signal φ instead of jJT]
11 is different in that it is made to have a 11" configuration, and other parts are the same, so the same reference numerals as in FIG. 2 are given.

9f% In the circuit shown in Figure 3, if the input signals A and B are both 1'' or both 10''1, the logic setting section 20 becomes conductive, the voltage at node X becomes the ground potential, and the control signal φ becomes When the voltage of transistor M1 is 11 level, the voltage at output node W becomes 1 level, and inverter circuit 2
The output signal F becomes R11+ level. In contrast, input signal A.

If either one of B is 11'11 and the other is 0'', one of the transistors N, , N is conductive;
the other is blocked. In this case, when the control signal j is 1, the voltage at the node
) 0 ・・・・・・・・・ (2) That is, VTHP,
<VTHMI (VDD ・・・・・・・・・・・・
... It is necessary to make sure that (3) holds true.

Figure 4 shows the load circuit using a negative resistance circuit.
, compared to the circuit in FIG. 3, the precharge transistor IJ3 is changed to a depletion type transistor, and a depletion type P-channel IJO8- is connected between the source of this transistor M1 and the VDD source. FET M
, is inserted and connected, and the gate of this transistor M4 is connected to the output node W. The other points are the same, so the same reference numerals as in FIG. 3 are given.

The operation of the circuit shown in FIG. 4 differs from the operation shown in FIG. has a low resistance, and the voltage at the output node W is held statically, so it does not decrease over time.On the other hand, when the control signal φ is 61" pulses and the voltage at the output node W is at ground potential ■, the load circuit becomes high resistance, and the current becomes very small. When the control signal 7 is at the "0" level, the load circuit has a low resistance regardless of the voltage at the output node W, and the output node Precharge W.

FIG. 5 typically shows a two-stage circuit in order to explain an example of inter-stage connection when a plurality of stages of the circuit shown in FIG. 4 are connected in series. Here, the first stage circuit is given the same reference numeral as the circuit in FIG. 4, and the part 0 corresponding to the first stage circuit of the next stage circuit is
The same reference numerals as those for the first stage circuit are appended with ''. In addition, CI
is the stray capacitance at the output node W of the first stage circuit, and %C2 is the gate-drain capacitance of the transistor P2' of the next stage circuit.

In the circuit of FIG. 5, input signals A and B are introduced to the first stage circuit in the same way as the circuit of FIG. The input signals are respectively guided to the gate of the transistor P1', and the output signal F (=A B) of the first stage circuit is guided to the gate of the transistor N2/, and the Lij node of the first stage circuit is guided to the gate of the transistor P2'. The voltage of W (=F=A■B) is directly guided. Therefore, the signal at the output node P of the next stage circuit becomes A3.C10.B-D. In this case, the problem is that the device side j signal 7 is “
This is a case where the input signal changes to the "0" level after reaching the "0" level, and the voltage force VDD -VTHMI' (where VT
HMI' changes from the threshold voltage of the transistor M (1% voltage) to the ground potential. At this time, the voltage at the output node H of the first stage circuit varies from VDD to earth (
VDDC, +VTHMI'C2) Low C, +C.

down. Therefore, at this time, the transistor P of the next stage circuit;
In order to be cut off, VDD −VTHM; ・・・・・・・・・・・・・
・・・・・・・・・・・・ It is necessary to make sure that f41 holds true. However, if a negative resistance +9J path is used in the load circuit as in the circuit shown in Fig. 5, the voltage at the output node W of the first stage circuit increases to VDD i over time.
Even if the above formula (5) does not hold, VTHlj') VTHP2'...
If (6) holds true, the electric current IE at the output node W' of the next stage circuit changes to Voo'J over time.

Note that each of the logic setting sections is not limited in the number of input signals; the deaf conducts when the logic condition of the result is satisfied with respect to the input signal, and is cut off otherwise. , enhancement) (4's first conductivity type (in this example, N channel) MO'S FgT and depression type's second conductivity type (the above 14 ilt type and (... reverse, in this example, P channel) It is sufficient if it is a 1ixiJ path in which +vos-FgT are connected together.

〔Effect of the invention〕

As mentioned above, according to the CMO8 dark circuit of the present invention,
It is possible to reduce the types of human input signals to the logic setting section, eliminate the need for attached circuits, improve operation, reduce circuit pattern area, and reduce costs. It is possible to realize cMOS jf:M circuits for watches, calculators, microcomputers, etc., which require lower prices.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing the conventional CM OS N611 old (-11 path), and Figures 2 to 5 are circuit diagrams each showing an LI example of the C117os ethical circuit related to misfire [!1]. is. N I + N 2 + Vr H+ Vr2 ・
・・Enforcement type N-channel IJO8-F
[DT, +v3...enhancement type P channel +aos-rrb'r. P1+P2... Debretsu 7 Yon l Cedar's P Chang IJO3-FET, 20... Logic setting section. Applicant's agent Patent attorney Rin, ``-yo Gutei 1tsu Figure 2 113 Figure 0 Figure 4

Claims (1)

[Claims] fil enhancement type first conductivity type MO8-FgT
and a depression type second conductivity type 15-FET, the circuit includes a logic setting section from which a plurality of logic operation input signals are guided, and a source terminal and a drain terminal at one end of the logic setting section and an output node, respectively. The first of the enhancement type is connected and the leveling voltage is applied to the gate.
/8 conductivity type @I MOS-FET, and a second 1JO8 of a second conductivity type, the drain terminal of which is connected to the output node, the source terminal connected to the operation source, and the open side j signal applied to the gate. -FBT, and at least when the control signal is at a predetermined logic level, the other end of the logic setting section is grounded (Sk
A C u'o S logic circuit comprising ground setting means for setting. (2) The front and ground setting means is an enhancement type first conductivity type MOS-FET whose drain terminal is connected to the other end of the logic setting section, whose source terminal is grounded, and whose gate is applied with the control signal. A CMOS logic circuit as described in Patent No. 1, characterized in that: (3) The ground setting means directly grounds the other end of the logic setting section, and the leveling pressure applied to the gate of the first MOS-FET is the narrow opening 111 signal. A Ck40S logic circuit according to claim 1. (4) The second 1.408-FET is of the depression type, and its source terminal is connected to the operating power supply via the fourth MOS-FET of the first conductivity type of the depression type, and this v, 7. The ClviOS logic circuit according to claim 1, wherein the gates of the No. 4 MOs-FETs are connected to the output node. (5) The voltage at the output node is led to the gate of the second conductivity type vOs-PET of the first logic setting section of the next-stage Chaos logic circuit, and the voltage at the output node is inverted by the inverter circuit. The first conductivity type of the logic setting section of the CIr40S logic circuit in the next stage is guided to the gate of the 40S-FET, and the control signal is also guided to the CMOS logic circuit in the next stage. A CMOS logic circuit in the patent race featuring the following.