JPS594033A - 圧接型半導体装置 - Google Patents

圧接型半導体装置

Info

Publication number
JPS594033A
JPS594033A JP57112975A JP11297582A JPS594033A JP S594033 A JPS594033 A JP S594033A JP 57112975 A JP57112975 A JP 57112975A JP 11297582 A JP11297582 A JP 11297582A JP S594033 A JPS594033 A JP S594033A
Authority
JP
Japan
Prior art keywords
cathode
substrate
groups
region
periphery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57112975A
Other languages
English (en)
Other versions
JPH0142498B2 (ja
Inventor
Minoru Azuma
東　実
Katsuhiko Takigami
滝上　克彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57112975A priority Critical patent/JPS594033A/ja
Priority to CS834851A priority patent/CS244676B2/cs
Priority to EP19830303809 priority patent/EP0098175A3/en
Publication of JPS594033A publication Critical patent/JPS594033A/ja
Publication of JPH0142498B2 publication Critical patent/JPH0142498B2/ja
Granted legal-status Critical Current

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  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置に係わシ、特に改良された圧接型電
極構造を有する大電流用の圧接型半導体装置に関するも
のである。
〔発明の技術的背景〕
通電電流が１０ＯＡを越えるような大電流半導体装置の
電極数シ出し方法は、小電流半導体装置で使われている
金属ワイヤぜンディング法を用いることができず、２つ
の主電極間に圧力を加えて取υ出す、いわゆる圧接型電
極を使っている０大電流半導体装俤゛の一例としてダー
トターンオフサイリスタ（以下ＧＴＯと１１！−ぶ）を
掲げ、図面を参照しながら従来装置について説明。
する。
第１図に従来のＧＴＯの断面図を示す。ＧＴＯ基板１は
Ｐ型アノード領域１１ｓ”型第１ペース領域１２、Ｐ型
第２ペース領域（ダート領域）１３、ｎ型カソード領域
１４の４層から成り、カソード領域１４は複数個に分割
されている。
一般に圧接構造では、この例のように、凹凸形状の凹部
にダートが、凸部にカンードが露出する。基板の一面に
は分割された複数個のカソード領域１４にそれぞれ接続
するカソード領域２及びカソード領域を囲むように配置
されたＰ型ゲート領域１３にはダート電極３が各々形成
され、基板の他方の面にはアノード電極４が形成されて
いる。アノード電極４には金属板５が接着され、これが
外囲器の金属ポスト６に接触する。複数のカソード電極
２は金属板７を介して外囲器の金属ポスト８に接触する
。ダート電極３には金属ワイヤ９が接着され、これが外
囲器のｆ−）端子に取シ付けられる。ＧＴＯは基板１の
端面に露出するｐＮ接合はシリコーンゴム、ガ怜 ラス等の絶縁物１０が婢覆される。
第１図に示すＧＴＯのように１カソード領域が複数個に
分割された素子は、各カソード電極下のｎＰｎＰ　４層
の半導体領域が１つの素子（素子ユニット）を構成し、
このような素子ユニットがカソード電極の数だけ配列さ
れていると考えられる。つマシ、素子ユニット同志は２
つのペース領域及びアノード領域間を各領域の固有抵抗
で結ばれ、各素子ユニットのカソード及びアノード電極
は共通なので、全体の素子は複数の素子ユニットの並列
動作とみなすことができる。このような素子の動作上好
適な条件としては、素子ユニット間の特性分布が均一な
ことはもとよシ、各カソード電極と外囲器の電極との接
触状態を良好に保つことである。というのは各カソード
間での圧力の相違は、接触抵抗の違いをもたらし特性分
布を不均一にするがらである。凍へ た、半導体基板を構過するシリコンの熱膨張係数と外囲
器電極を構成するモリブデン等の金属板のそれが異なる
ため、動作時に素子で発生する熱により、両者の間にす
べり丑さっが平面の中心から外側に向けて発生する。一
般に半導体基板の電極はアルミニウム等の比較的軟らか
い金属が用いられるので、半店、体基板の電極は外囲器
側のモリブデン等の比較的硬い金属にこすられて薄板状
に押し出され、ダート電極に接触する短絡事故を引き起
こすことがある・従って従来は以上の問題点を考慮して
、カソードを基板の中心から外側へ、つまり放射状に分
散配置する構造が用いられている。
第２図にＧＴＯ基板１の模式的平面図を示す。
ＧＴＯ基板１表面の複数に分割された矩形状カソード領
域１４は、図示の如く中央から周辺に放射状をなして配
置される。図の場合、基板を径方向にＡ、Ｂ、Ｃの３つ
の領域に分けて各領域にカソード群が配置されている。
〔背鼠技術の問題点〕
前記したように半導体基板のカソード電極と金属板の接
触における問題点は、カソード領域を放射状に分散配置
することでかなりの問題点が解決できたが、この放射状
構造で新たな問題が生じた。第２図におけるＡ領域のよ
うに基板面の外周部に位置する群のカソードは、隣シ合
うカソード間距離がカソードの長さ方向にわたってほぼ
一様に保たれるのに対し、Ｃ領域のように基板面の中央
部に位置するカソードは、長辺の長さが外周部と同じで
あるから、隣シ合うカソード間距離は中心に近い程小さ
く、中心から離れる程太きい。Ｃ領域のカソード間隔が
大きい箇所では、各カソードで狭まれるゲート部が他領
域に比べて広くなる。これら２つの場合において各々金
属板７を介して圧力を印加した場合、第３図の（ａ）　
、　（ｂ）のようになる。同図のＯｆｄ　Ａ領域に、（
ｂ）はＣ領域のカソード間隔が太きい箇所に各々対応す
る。図から明らかなように（、）の場合はカソード間隔
ｒが小さいため、金属板のたわみ量ｌが小さいが、（ｂ
）ではｒが太きいためｌが太きい。ｌがツＪンード・ダ
ートの段差ｙを越えれば、金属板７シよケ゛−ト電極３
に接触することになシカソード・ダート間は短絡する。
金属板７としては、通常圧力印加によって塑性変形を起
こさない硬質なモリブデン等が使われる。また各カソー
ド電極と均一に接触するには金属板７は比較的薄い方が
よく通常ｓ　ｏ　ｔｔｍ乃至１閣厚が用いられる。
第４図には金属板７として厚さが５０μｍと２００　Ｊ
ｉｍのモリブデン板を用いた場合、３００　ｋｇ／ｃ１
ｎ　”の圧力を印加した時のｒとｌの関係を示す。カソ
ード・ダートの段差が２０μｍあっても、モリブデン板
の厚さが５０μｍではカソード間隔が１調を越えるとモ
リブデン板ｔｉ段差の底部、即ちｒ−）電極に接触し、
カソード・ダート間の短絡をひき起す。
〔発明の目的〕
本発明は、上記問題点についてなされたもので、ｆＩＪ
１々の電気的特性を損なうことなく、信頼性を改善しう
る圧接型半導体装置の構造を提供するものである。
〔発明の概要〕
本発明は、圧接型半導体装置において前述のように複数
のカソードまたはエミッタ領域を基板中央から周辺に放
射状に分散配置する場合に、基板中央に配置される群の
カソード捷たはエミッタ領域の長辺を周辺に配置される
群のそれより短く設定することにより、隣接するカソー
ド間隔が基板中央部の群においても大きくならないよう
にする。
〔発明の効果〕
本発明によれば、金属板を加圧接触させた場合の前述し
たような金属板のたわみによる基板中火部でのカソード
・ダート間短絡が確実に防止され、圧接型半導体装置の
信頼性向上が図られる。また本発明によれば、基板中央
部で、短いカソード領域を配列することによりカソード
占有率が大きくなる結果電流密度が小さくなり、平均順
電流、オン電圧、サージ電流耐量などが改善され、更に
外囲器上の間の熱抵抗が下がるといった効果が得られる
。
〔発明の実施例〕
第５図に本発明の一実施例のＧＴＯ基板の模式的平面図
を示す。断面構造は第１図と異ならないので説明を省略
する。ＧＴＯ基板３ｏは矩形状をなす複数に分□離され
たカソード領域３１とそれらを囲むように配置されたダ
ート領域３２から成る。カソード領域にはカソード電極
が、ダート領域にはｆ−ト電極がそれぞれ接続される。
ダート電極の取シ出しリード線３３は図の場合基板の周
辺部に接続しているが、中心部であってもよい。基板面
は径方向にＡ−Ｅ領域に分けられ、各領域にカソード群
が配置されている。
そして基板の中心領域にあるカソード群は、それよシ周
辺の領域にあるカソード群に比べて、各カソード領域の
長辺が短い。ＧＴＯ基板３ｏの端面に露出するＰＮ接合
はシリコーンゴム、ガラス等の絶縁物３４゛で被覆され
る。
次に具体的な数値例を説明する。第６図は第５図の中央
部分から２つの領域り、Ｅのカソード配置を拡大して示
している。ＧＴＯ基板の中心から１間の位置から１．５
　ｔｔａｎの位置にかけて長さ０、５　ｔｍの第１のカ
ソード群（領域Ｅ）が配置される。′その時最も中心に
近り部分のカソード間隔は０．２　ｔｍ　、最も中心か
ら遠い部分のカソード間隔は０．４８ｍｍで、カソード
幅は０．３　ｔｔｔｍである。
第２のカソード群（領域Ｄ）は中心から２諺の位置から
３鴫の位置にかけてあり、それらの長、さけ１閣である
。第２のカソード群の最も中心に近い部分のカソード間
隔は０．２　ｔａｎ　１最も遠い部分のカソード間隔は
０．４５霧であシ、カソード幅は０．３　ｍｍで第１の
カソード群のカソードと同じである。以下第３、第４等
のカソード群は上記と同様に設計される。即ち基板の中
心からｒｌの位置からｒ２の位置にかけて配置されるカ
ソード群において（ｒ２／ｒｌ）の値をある値よシ小さ
くすれば、カソード間隔をある値以下に設定できる。こ
の実施例では（ｒ２／ｒ１）を１．５以下、カソード間
隔を０．４８　ａｍ以下にしである。
このようなカソード配置をすれは、金属板を圧接したと
きにそのたわみ量が抑えられ、一般的な電気特性を何ら
損なうことなくカソード・ダート間の短絡をなくすこと
ができる。ちなみに、上記実施例における２０個のＧＴ
Ｏについて、カソード・ダート短絡は一つもなかった。
それに対して従来の第２図のようなカソード配置のＧＴ
Ｏでは、ｒｌが１ｓ＋Ｓ　ｒ２が５咽のものはカソード
間隔が約２瓢になシ、ダート上をポリイミド等の絶縁物
で保護しないと２０個中種２個が短−絡した。また絶縁
物で保護しても金属板に点在する突起等で絶縁物が破ら
れ短絡が起こシ、この例では２０個中種個が短絡した。
また本実施例によれば、基板の中心部に短いカソードを
配列することにより、カン−ｒの占積率が大きくなるの
で電流密度が小さく彦り、平均順電流、オン電圧、サー
ジ電流耐量が改善されるｔｌか、外囲器との間の熱抵抗
が下がる長所が生まれる。
なお本発明は、ＧＴＯのほかに、圧接型の／４’ワート
ランジスタ等のカソードまたはエミッタが分離配置され
るものに同様に適用できることはもちろんである。
【図面の簡単な説明】
第１図は従来のＧＴＯの断面図、第２図は従来のＧＴＯ
基板の平面図、第３図（−）　（ｂ）はＧＴＯ基板のカ
ソード側金属板のたわみの様子を示す断面図、第４図は
カソード間隔とたわみ量の関係を示す図、第５図は本発
明の一実施例におけるＧＴＯ基板の平面図、第６図はそ
の部分拡大平面図である。 ３０・・・ＧＴＯ基板、３１・・・カソード領域、３２
・・・ダート領域。 出願人代理人　弁理士　鈴　江　武彦 第５図 −１６０− 第６図 １ １ｍｍ　　ｒ、　　ｒ２

Claims (1)

    【特許請求の範囲】
  1. 半導体素子基板の一方の主面に溝により分離された矩形
    状の複数のカンードまたはエミッタ領域が基板中央から
    周辺に放射状に分散配置された圧接型半導体装置におい
    て、前記複数のカンードまたはエミッタ領域は、基板中
    央に配置される群におけるものの長辺が周辺に配置され
    る群のそれよシ短く設定されていることを特徴とする圧
    接型半導体装置。
JP57112975A 1982-06-30 1982-06-30 圧接型半導体装置 Granted JPS594033A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP57112975A JPS594033A (ja) 1982-06-30 1982-06-30 圧接型半導体装置
CS834851A CS244676B2 (en) 1982-06-30 1983-06-29 Semiconductor element with press contact
EP19830303809 EP0098175A3 (en) 1982-06-30 1983-06-30 Pressure contact type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57112975A JPS594033A (ja) 1982-06-30 1982-06-30 圧接型半導体装置

Publications (2)

Publication Number Publication Date
JPS594033A true JPS594033A (ja) 1984-01-10
JPH0142498B2 JPH0142498B2 (ja) 1989-09-13

Family

ID=14600244

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57112975A Granted JPS594033A (ja) 1982-06-30 1982-06-30 圧接型半導体装置

Country Status (3)

Country Link
EP (1) EP0098175A3 (ja)
JP (1) JPS594033A (ja)
CS (1) CS244676B2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03119762A (ja) * 1989-10-02 1991-05-22 Toshiba Corp 電力用圧接型半導体装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60194565A (ja) * 1984-03-15 1985-10-03 Mitsubishi Electric Corp 半導体装置
DE58903790D1 (de) * 1988-08-19 1993-04-22 Asea Brown Boveri Abschaltbares halbleiterbauelement.
JP2739970B2 (ja) * 1988-10-19 1998-04-15 株式会社東芝 圧接型半導体装置
EP0380799B1 (de) * 1989-02-02 1993-10-06 Asea Brown Boveri Ag Druckkontaktiertes Halbleiterbauelement
JP2502386B2 (ja) * 1989-04-11 1996-05-29 富士電機株式会社 半導体装置
DE69312865T2 (de) * 1992-11-09 1998-01-22 Delco Electronics Corp Vertikale PNP Halbleiteranordnung
US7675903B2 (en) 2004-02-06 2010-03-09 Alcatel Lucent Dynamic contact list management system and method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57201077A (en) * 1981-06-05 1982-12-09 Hitachi Ltd Semiconductor switching device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4035831A (en) * 1975-04-17 1977-07-12 Agency Of Industrial Science & Technology Radial emitter pressure contact type semiconductor devices
DE2757821C3 (de) * 1976-12-28 1982-08-19 Tokyo Shibaura Electric Co., Ltd., Kawasaki, Kanagawa Verfahren zur Herstellung einer Mesa-Halbleiteranordnung mit Druckkontakt
FR2378354A1 (fr) * 1977-01-19 1978-08-18 Alsthom Atlantique Procede de fabrication de semiconducteurs de puissance a contacts presses
DE2902224A1 (de) * 1979-01-20 1980-07-24 Bbc Brown Boveri & Cie Kontaktsystem fuer leistungs-halbleiterbauelemente

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57201077A (en) * 1981-06-05 1982-12-09 Hitachi Ltd Semiconductor switching device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03119762A (ja) * 1989-10-02 1991-05-22 Toshiba Corp 電力用圧接型半導体装置

Also Published As

Publication number Publication date
CS485183A2 (en) 1985-08-15
CS244676B2 (en) 1986-08-14
EP0098175A3 (en) 1985-10-23
JPH0142498B2 (ja) 1989-09-13
EP0098175A2 (en) 1984-01-11

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