JPS5936248U - Resin mold semiconductor device - Google Patents
Resin mold semiconductor deviceInfo
- Publication number
- JPS5936248U JPS5936248U JP1982129219U JP12921982U JPS5936248U JP S5936248 U JPS5936248 U JP S5936248U JP 1982129219 U JP1982129219 U JP 1982129219U JP 12921982 U JP12921982 U JP 12921982U JP S5936248 U JPS5936248 U JP S5936248U
- Authority
- JP
- Japan
- Prior art keywords
- lead
- heat dissipation
- common
- dissipation board
- portions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の樹脂モールド半導体装置を示す平面図、
第２図は第１図の■−■線に相当する部分の断面図、第
３図はモールド後の状態を示す平面図、第４図はモール
ド樹脂体のそりを示す正面図、第５図は本考案の第１の
実施例のリードフレームを示す平面図、第６図は第５図
のリードフレームを屈曲した状態を示す平面図、第７図
は第６図の■−■線を示す断面図、第８図は第６図のリ
ードフレームを使用したモールド半導体装置をモールド
前の状態で示す平面図、第９図は第８図のＩＸ−ＩＸ線
に相当する部分を示す断面図、第１０図は本考案の第２
の実施例に係わるモールド半導体装置を示す平面図、第
１１図は第１０図のＸＩ−ＩＸ線に相当する部分を示す
断面図、第１２図は本考案の第３の実施例に係わるモー
ルド半導体装置を示す平面図、第１３図は第１２図のｘ
ｍ−ｘｍ線に相当する部分を示す断面図である。
尚図面に用いられている符号に於いて、１はトランジス
タチップ、２は放熱基板部分、３は独立コレクタリード
部分、４は内部リード部材、５は独立ベースリード部分
、６は共通エミッタリード部分、７は内部リード部材、
８は内部リード接続用導体部分、９はモールド樹脂体、
１３は屈曲部である。
第６図 β
■−
■−
Ｊｌ、−FIG. 1 is a plan view showing a conventional resin molded semiconductor device;
Figure 2 is a cross-sectional view of the portion corresponding to the line ■-■ in Figure 1, Figure 3 is a plan view showing the state after molding, Figure 4 is a front view showing warpage of the molded resin body, and Figure 5. 6 is a plan view showing the lead frame of the first embodiment of the present invention, FIG. 6 is a plan view showing the lead frame shown in FIG. 5 in a bent state, and FIG. 7 shows the line ■-■ in FIG. 6. 8 is a plan view showing a molded semiconductor device using the lead frame shown in FIG. 6 in a state before molding; FIG. 9 is a sectional view showing a portion corresponding to line IX-IX in FIG. 8; Figure 10 is the second version of this invention.
FIG. 11 is a sectional view showing a portion corresponding to the line XI-IX in FIG. 10, and FIG. 12 is a plan view showing a molded semiconductor device according to a third embodiment of the present invention. A plan view showing the device, Fig. 13 is the x of Fig. 12.
It is a sectional view showing a part corresponding to the m-xm line. In the symbols used in the drawings, 1 is a transistor chip, 2 is a heat dissipation board part, 3 is an independent collector lead part, 4 is an internal lead member, 5 is an independent base lead part, 6 is a common emitter lead part, 7 is an internal lead member;
8 is a conductor part for connecting internal leads, 9 is a molded resin body,
13 is a bent portion. Figure 6 β ■− ■− Jl, −
Claims (1)
立リード部分と同一方向に導出された部分を有する共通
リード部分と、 前記独立リード部分が導出されている側と反対の側に於
いて前記複数の放熱基板部分に沿うよう番Ｈ配置され且
つ前記共通リード部分に連続するように設けられてい乙
共通の内部リード接続用導体部分と、 前記複数の放熱基板部分の表面に夫々固着された複数の
半導体チップと、 前記複数の半導体チップと前記共通の内部リード接続用
導体部分とを夫々電気的に接続する複数の内部リード部
材と、 前記複数の放熱基板部分、前記複数の半導体チップ、前
記複数の内部リード部材、及び前記複数の独立リード部
分と前記共通リード部分との少なくとも一部を被覆する
ように設けられ且つ前記放熱基板部分の裏面側の樹脂層
よりも表面側の樹脂層が厚くなるように設けられている
か又は前記放熱基板部分の裏面が露出するように設けら
れているモールド樹脂体と を少なくとも有する半導体装置に於いて、前記共通リー
ド部分を屈曲することによって前記共通の内部リード接
続用導体部分を前記複数の放熱基板部分と同一平面に配
置せずに前記複数の放熱基板部分の前記表面側に片寄ら
せて配置したことを特徴とする樹脂モールド半導体装置
。[Claims for Utility Model Registration] A plurality of heat dissipation board portions arranged in parallel, a plurality of independent lead portions led out in the same direction, and a common lead portion having a portion led out in the same direction as the independent lead portions; A number H is arranged along the plurality of heat dissipation board parts on the side opposite to the side from which the independent lead parts are led out, and is provided so as to be continuous with the common lead part B, for connecting a common internal lead. a conductor portion; a plurality of semiconductor chips respectively fixed to the surface of the plurality of heat dissipation board portions; and a plurality of internal leads electrically connecting the plurality of semiconductor chips and the common internal lead connection conductor portion, respectively. a member, provided so as to cover at least a portion of the plurality of heat dissipation board parts, the plurality of semiconductor chips, the plurality of internal lead members, the plurality of independent lead parts and the common lead part, and the heat dissipation member. A semiconductor device having at least a molded resin body in which a resin layer on a front side of the substrate portion is thicker than a resin layer on a back side of the substrate portion, or a molded resin body is provided so that the back side of the heat dissipation substrate portion is exposed. By bending the common lead portion, the common internal lead connecting conductor portion is not disposed on the same plane as the plurality of heat dissipation board portions, but is shifted toward the surface side of the plurality of heat dissipation board portions. A resin molded semiconductor device characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982129219U JPS5936248U (en) | 1982-08-27 | 1982-08-27 | Resin mold semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982129219U JPS5936248U (en) | 1982-08-27 | 1982-08-27 | Resin mold semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5936248U true JPS5936248U (en) | 1984-03-07 |
| JPS629735Y2 JPS629735Y2 (en) | 1987-03-06 |
Family
ID=30292857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1982129219U Granted JPS5936248U (en) | 1982-08-27 | 1982-08-27 | Resin mold semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5936248U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013239659A (en) * | 2012-05-17 | 2013-11-28 | Sumitomo Electric Ind Ltd | Semiconductor device |
-
1982
- 1982-08-27 JP JP1982129219U patent/JPS5936248U/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013239659A (en) * | 2012-05-17 | 2013-11-28 | Sumitomo Electric Ind Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS629735Y2 (en) | 1987-03-06 |
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