JPS59219027A - Pll circuit - Google Patents

Abstract

PURPOSE:To form an oscillating signal in a minute step with simple constitution by providing a pulse integration counter counting respectively a reference frequency unit and a unit less than the reference frequency unit and a D/A converter for a numerical value less than the unit. CONSTITUTION:An added pulse is transmitted to a pulse integration counter 13 from an adjusting device 19 through the operation of the frequency adjusting device 19. The 2nd digit part 16 of the counter 13 integrates the added pulse, and when a digit d1 less than this digit is carried by integration, a digit d2 less than the 2nd digit is counted and values up to a digit dm less than the digit (d) are integrated sequentially by (m). When the less digit dm is carried, a unit digit D1 of the 1st digit part 15 is counted and the value up to the unit digit Dn is integrated sequentially. When the input of the added pulse is lost, the digit parts 15, 16 output respectively its numeral to a program counter 7 and a D/A converter 20. A reference frequency generating circuit 21 increases the frequency of a reference signal fr in response to an analog signal DELTAV from the converter 20 and inputs the result to a phase comparator 3, where the phase is compared with the phase of a frequency-divided signal fd from the counter 7 and a voltage controlled oscillator 5 is controlled by a signal smoothing the compared output with an LPF4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PLL circuit, and particularly to a PLL circuit that generates an oscillation signal in steps less than a reference frequency unit.

Generally, the oscillation signal f is a step-by-step oscillation signal f in units of a reference frequency. To output from the voltage controlled oscillator 5 (hereinafter referred to as VCO), as shown in FIG. The frequency and phase of the reference signal fr generated in step 2 are compared by a phase comparator 3. In FIG. 1, reference numeral 4 is a low f-s filter, l is a crystal oscillator, and 6 is an output terminal.

Communication transceivers and the like generate oscillation signals in minute steps less than a reference frequency unit. In this case, disconnect the dotted line in Figure 1 and connect the mixer 8 without connecting the Z' point.
connect to the return path. The mixer 8 injects the dilocal signal fL by the first method of connecting the X point or the second method of connecting the Y point. In the first method, a separate PL
The output of the L circuit 10 is injected into the mixer 8 via the fixed splitter 9 and the connection at the X point. The PLL circuit 10 includes a crystal oscillator 10a, a reference frequency generation circuit 10b, a phase comparator 10c, a low-pass filter 10d, and a VCO 1.
0e glogramma pull counter 10f is provided. Second
In this method, the digits below the reference frequency are converted by the digital-to-analog converter 12 and output as an analog signal to the vco i i. The VCO 11 oscillates a local signal according to the analog signal and injects it into the mixer 8 via a Y connection.

The first method or the second method described above has drawbacks such as high cost due to the complicated circuit configuration.

In view of the above-mentioned points, the present invention is based on Af7:,
The first thread I] is applied to fine-step channels in communications transceivers, etc., and is suitable for practical use with a simple circuit configuration.
The purpose is to provide an LL circuit.

The present invention provides a pulse integration count having a first digit part for counting reference frequency units and a second digit part for counting less than the reference frequency units, and a Noculus integration count.
The configuration includes digital-to-analog converting means for converting the numerical value of the second digit part of 'fC into an analog quantity, and reference frequency changing means for changing the reference frequency according to the analog quantity.

Hereinafter, one embodiment of the PLL circuit according to the present invention will be described in detail with reference to FIG.

In FIG. 2, 21 is a reference frequency generation circuit. The reference frequency generation circuit 21 is composed of a crystal oscillator, a variable reactance element, and a frequency dividing circuit, and outputs a reference signal fr to the phase comparator 3. The frequency of the reference signal fr is in reference frequency units. When the analog signal Δ■ is input from the digital-to-analog converter 20, the frequency of the reference signal fr increases in accordance with the analog signal ΔV.

- The glucose integration counter 13 is composed of a first digit part 15 and a second digit part 16. Second digit part 15
has the first less than digit dlsM2, less than m digit d2, . The first digit part 15 is the first unit digit D
1. ．． Has a second unit digit D2...mu1n unit digit Dn,
The first unit digit Dl is the minimum digit, and the n111th digit Dn is the maximum digit. (Each digit of -C is a decimal number for explanation.) Frequency adjuster 19 '' (When operated, an addition pulse or a subtraction pulse is sent from the frequency adjuster 9 to the terminal 14. - When the signal is sent to the terminal 14, the pulse integration counter 13 adds N, 't9. When the first digit below dB is carried up during the integration, the second digit below d2 is counted. The m-th digit dm is sequentially integrated up to the m-th digit am. When the m-th digit dm is raised to tf, the first unit digit DI is counted, and it is sequentially integrated up to the m-4n unit digit Dn. When no input is received, the pulse integration counter 13 stops counting and the first digit part 15
The numerical value is output to the programmable counter via the unit digit path 17. The value of the second digit part 16 is 11~
Output to digital-to-analog converter 20 via digit bus 18. Note that the numerical values on the unit digit bus 17 and the unused digit bus 18 can be monitored with a count display (l in the figure).

The digital-to-analog converter 20 converts the numerical value of the second digit part 16 of the second digit part 16 through the fractional digits 18 and outputs it to the reference frequency generation circuit 21 as an analog signal ΔV.

Here, the first unit digit D! Our standard frequency unit is 101c.
Hz, and if the change frequency Δf for less than mth digit dm is 1/100,000 of the reference frequency unit of 10 kHz, then mth
When the less than digit is 1, the reference signal fr is 10 kHz +0
．． 1 Hz N 9: 10 kHz + 0.9
Hz. By operating the frequency adjuster 19, the n-th unit digit Dn, ... the first unit digit DI, and the less than m-th digit dm.
...The first digit dl is "10000 and 000...
When set to ``, the oscillation signal f becomes 100.00 MHz. When set to 10000 and 100...'', the oscillation signal f becomes 100.00 MHz. is 100.001 MHz. -100
100.009MH when set to 00 and 900-”
It becomes z. When set to 10001 and 00...'', the oscillation signal fr becomes a step of 10001 times the reference frequency unit, that is, 100.01MHz.Oscillation signal f
. The frequency of is 100.00 MI (z~100.01
It changes continuously between MHz according to the operation of the frequency adjuster 14. It is also possible to change continuously between other reference frequency units in the same way. Note that when the ratio between the minimum value and the maximum value of the frequency division ratio of the programmable counter 7 becomes large, a slight error occurs.

The PLL circuit according to the present invention has a pulse integration counter having a first digit part for counting reference frequency units and a second digit part for counting less than the reference frequency, and converts the numerical value of the second digit part into an analog value. digital-to-analog conversion means;
Since it is configured to include a reference frequency changing means that changes the reference frequency according to the analog quantity, it has the feature that the reference frequency can be changed continuously according to a numerical value less than the reference frequency. To continuously obtain a stable oscillation signal without damaging the mutual operation characteristics of each part circuit of a PLL circuit. In addition, since the circuit configuration is simpler than that of the conventional circuit, manufacturing costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional PLL circuit, and FIG. 2 is a block diagram showing an embodiment of the PLL circuit according to the present invention. In the figure, reference numeral 1 is a crystal oscillator, 2 and 21 are reference frequency generation circuits, 3 is a phase comparator, 4 is a ronos filter, 5 is a voltage controlled oscillator, 6 is an output terminal, 7 is a glogram pull counter, 8 is a mixer, 9 is a fixed splitter, IO is PLI,
circuit, ll is VCO112 is digital analog converter,
13 is a pulse product event counter, 14 is a terminal, and 15 is a first
digit part, 16 is the second digit part, 17 is the unit digit,
18 is a lower digit path, 19 is a frequency adjuster, and 20 is a digital-to-analog converter. Patent applicant: Yaesu Musen Co., Ltd. Figure 1 Figure 2

Claims (1)

[Claims] 1. A voltage controlled oscillator that outputs an oscillation signal in steps of the reference frequency, and a frequency of the oscillation signal of 15? PL equipped with a programmable counter that divides the frequency at a fixed frequency division ratio
In the L circuit, a pulse integration counter has a first digit part for counting the reference frequency unit and an M2 digit part for counting less than the reference frequency unit, and converts the numerical value of the second digit part into an analog quantity. It is characterized by comprising a digital-to-analog conversion means and a reference frequency changing means for changing the reference frequency according to the analog amount, and configured to determine the frequency division ratio by the numerical value of the first digit. PLL circuit.