JPS5918757Y2 - Frequency synthesizer using PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency synthesizer using a phase-controlled loop (PLL) circuit.

As a frequency synthesizer using a conventional PLL circuit,
A voltage controlled oscillation circuit (hereinafter referred to as VCO) of a PLL circuit.

), a phase comparison circuit, and a variable frequency divider used as a programmable counter.

Let fc be the input frequency of the phase comparator circuit, fo be the output frequency of the VCO, and N be the frequency division number of the variable frequency divider.

The variable frequency divider divides the VCO output by N to obtain the frequency fO/N.
generates the output of

The phase comparison circuit inputs the input signal of the frequency fc and the signal of the frequency fO/N from the variable frequency divider, and gives a signal based on the comparison result to the VCO, and as a result, the frequency of both input signals is fO/N. vCO is controlled so that and fc are equal.

That is, fo2Nfc. Here, the step frequency fo of the change in the output frequency fo is as follows.

That is, the step frequency ΔfO becomes equal to the input signal frequency fc of the phase comparison circuit.

Therefore, in order to reduce the step frequency Δfo, the input signal frequency fc of the phase comparator circuit must also be reduced in proportion to it.

By the way, the signal phase lock of the output of the VCO is performed at the input frequency fc of this phase comparator circuit.

Therefore, as described above, when fc becomes small, a problem arises in that the accuracy of the VCO output decreases.

In order to solve such problems, it is an object of the present invention to provide a frequency synthesizer using a PLL circuit that allows the phase comparison circuit input frequency to be relatively large even if the step frequency Δfo is sufficiently small.

To this end, the frequency synthesizer using a PLL circuit according to the present invention includes a reference frequency signal generation circuit that generates a reference frequency signal of a predetermined frequency, a voltage controlled oscillator whose output signal frequency is controlled by an input voltage, and the voltage controlled oscillator. a first variable frequency divider that frequency divides the output signal of the reference frequency signal, a second variable frequency divider that frequency divides the reference frequency signal, and a phase comparison of the outputs of the first and second variable frequency dividers. and a phase comparison circuit that outputs a signal according to the comparison result to the voltage-controlled oscillator, and the frequency division numbers of the first and second variable frequency dividers are set to N and N+n (n is a constant integer), respectively. and N is n
It is set sufficiently larger than .

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a first embodiment of the invention.

The device of this embodiment includes a reference frequency oscillation circuit 1, a programmable counter 2 used as a variable frequency divider, a phase comparison circuit 3, a loop filter 4, a voltage controlled oscillation circuit (VC
O) 5 and a programmable counter 6 used as a variable frequency divider.

The output frequency of the reference frequency oscillation circuit 1 is fr, and the VCO
The output frequency of programmable counter 2 is fo, and the output frequency of programmable counter 2 is
Let M and N be the frequency division numbers of and 6.

A programmable counter 2 divides the output of the reference frequency oscillation circuit 1 with a frequency fr to generate a signal with a frequency f/M.

This becomes the input signal to the phase comparison circuit 30.

Let the frequency f/M of this human signal be fc.

On the other hand, a programmable counter 6 divides the frequency of the signal of the frequency fo from the VCO 5 to generate a signal of the frequency fO/N.

The phase comparator circuit 3 compares the signal of this frequency fo/N with the input signal (fc=fr/M) and outputs a signal based on the comparison result.

The output signal of this phase comparator 3 is given to the VCO 5 as a voltage signal via a loop filter 4.

The output frequency fo of this VCO 5 is controlled by the voltage signal.

Here, the phase comparison circuit 3 generates an output so that the input frequency fc (fr/M) and the signal fo/N are equal.

Therefore, the output frequency fo is becomes.

The frequency division number M of programmable counter 2 is N-)-n (
n is a constant integer and is sufficiently smaller than N.

That is, N>n). In other words, the frequency division number of programmable counter 2 is equal to that of programmable counter 6.
It changes according to the frequency division number, and the difference is always set to a constant value.

A step frequency Δfo of change in the output frequency fo is determined.

When the frequency division number of the programmable counter 6 is N and N+1, the output frequencies of the VCO 5 are fo and fl, respectively.
Then, the human frequency fc of the r phase comparator circuit 3 is N+.

, which is approximately N times the step frequency Δfo,
It becomes sufficiently large compared to the step frequency.

In addition, when the output oscillation frequency is several tens of MHz or more, the second
In order to reduce the input frequency to the programmable counter 6 as in the second embodiment of the present invention shown in the figure, the VCO 5
It is preferable to provide a 17P prescaler 7 between the output of the programmable counter 6 and the programmable counter 6.

The output frequency fo at this time is fo=-Σ-・P・1,2
□.

Table 1 below shows the output frequency fo when using the synthesizer shown in the second figure.
A specific numerical example will be shown to explain the relationship between the frequency division number N, N-1-n, and the human frequency fc of the phase comparator circuit 3.

Here, the output frequency fo is: 100 MHz±50
It is set in the range of 0 Hz, and the step frequency Δfo is 100 Hz.

The frequency division number P of the Pnoscaler 7 is set to 4, and the reference frequency is set to 2.
It is 5.025 MHz.

As is not clear from Table 1, according to the present invention, even when obtaining a high frequency output with a small step frequency, the input frequency to the phase comparator circuit 3 can be made sufficiently high.
Good S/N ratio of the L circuit can be maintained.

In addition, in the example of Table 1 above, N2 is set to 1000, so as N moves away from 1000, the step frequency ΔfO becomes 10.
0 Hz, and the output frequency fO also deviates from the desired value by a maximum of f3Hz, but this amount is less than the output frequency f
o is 3xlOs, which is within the frequency error of the crystal used as the reference frequency oscillation circuit 1 and often causes no problem at all.

Further, Table 2 shows an example in which the step frequency Δfo is added in a geometric series.

As explained above, according to the present invention, the frequency division number of the variable frequency divider in Table 1 is set to N, the frequency division number of the second variable frequency divider is set to N+n, and the value N is made sufficiently larger than n. Even if the step frequency is made sufficiently small, the phase comparator input frequency can be made relatively large.

Therefore, ■OC's output frequency f.

This has the advantage that the phase can be maintained with high accuracy.

Further, since the above effect can be obtained by simply adding two variable frequency dividers, there is an effect that the configuration is simplified.

[Brief explanation of the drawing]

1 and 2 are diagrams respectively showing a first embodiment and a second embodiment of a frequency synthesizer using a PLL circuit according to the present invention.

Claims (1)

[Claims for Utility Model Registration] A reference frequency signal generation circuit that generates a reference frequency signal of a predetermined frequency, a voltage-controlled oscillator whose output signal frequency is controlled by an input terminal, and a circuit that separates the output signal of the voltage-controlled oscillator. a first variable frequency divider that divides the reference frequency signal, a second variable frequency divider that divides the reference frequency signal, and a phase of the outputs of the first and second variable frequency dividers,
A phase comparison circuit outputs a signal according to the comparison result to the voltage-controlled oscillator, and divides the frequency division numbers of the first and second variable frequency dividers into N and N-)-n (n is constant). A frequency synthesizer using a PLL circuit, characterized in that N is set to be sufficiently larger than n.