JPS5815334A - Phase locking type frequency synthesizer - Google Patents

Abstract

PURPOSE:To realize a minimum frequency variable step having smaller frequency than an output frequency of a reference signal generator, while keeping an excellent phase noise characteristic, by controlling the counting value of a programmable frequency divider and the phase shift amount of a voltage controlled phase shifter with a logial circuit. CONSTITUTION:An output signal of a voltage controlled oscillator 1 is branched into two, one is taken as a device output OUT and another is applied to a programmable frequency divider 2. The signal is stepped down in frequency and given to one input of a frequency phase comparator 3. An output signal of a reference signal generator 14 is applied to another input of the comparator 3 via a voltage controlled phase shifter 11 to compare the frequencies and phases of the both. An obtained error signal is negatively fed back to a frequency controlling terminal of the oscillator 1 via a loop filter 5. The counting value of the frequency divider 2 and the phase shifter amount of the phase shifter 11 are controlled with an output data of a logical circuit 13. A DA converter 12 converts an output of a logical circuit 13 into an analog signal and gives to the phase shifter 11.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in phase-locked frequency synthesizers. In particular, it relates to a frequency synthesizer having a frequency variable step smaller than the output frequency of the reference signal generator.

Indirect control station wave number synthesizers using phase synchronization technology have been put into practical use. FIG. 1 is a block diagram of a conventional frequency synthesizer of this type. A conventional frequency synthesizer branches the output signal of the voltage controlled oscillator 1 into two, one of which is output from the device as OUT, and the other is frequency-downgraded by a count value N by a programmable frequency divider 2 and then input to one of the inputs of the frequency phase comparator 3. supply to. The output of the reference signal generator 4 is given to the other input, the frequency and phase of both are compared, and the obtained error signal is passed through the loop filter 5 that determines the loop characteristics to control the frequency of the voltage controlled oscillator. Negative feedback is provided to the terminal to stably control the output frequency of the voltage controlled oscillator 4.

In such a circuit, the output frequency f. is determined by fJ=ToyR (1), where the output frequency of the reference signal generator 4 is the count value fN of the fR1 glogram pull divider.

In this way, the conventional same-wavenumber synthesizer changes the output frequency fR in the minimum variable step by externally controlling the count value of the programmable splitter, but if it is necessary to reduce this minimum variable step, KFi, the standard It becomes necessary to reduce the output frequency of the signal generator correspondingly to the step, resulting in the following technical disadvantages.

(1) The loop bandwidth of the negative feedback loop is preferably set to about 1710 of the reference signal frequency in order to ensure loop stability and reduce the degree of phase modulation due to the phase comparison frequency component for the output signal. If the loop bandwidth is made smaller in proportion to the decrease in , the amount of improvement in phase noise near the carrier of the output signal of the voltage controlled oscillator decreases, resulting in deterioration of the phase noise characteristics of the output signal near the carrier.

(2) Compared to the phase modulation index for the output frequency, the gold phase modulation index at the phase comparison frequency is I/NK, but when the loop bandwidth and output frequency of the negative feedback loop are constant and the reference signal frequency is made small , the count value N of the programmable frequency divider increases in inverse proportion to the reference signal frequency, the detection sensitivity of the frequency phase comparator to the phase modulation of the output signal decreases, and the detected voltage of the frequency phase comparator and the frequency phase comparison decrease. The ratio to the so-called residual noise voltage inherent in the device deteriorates. Therefore, the residual noise voltage of the frequency phase comparator cannot be ignored. In other words, when the reference signal frequency is lowered, the near-carrier phase noise of the output signal is determined by the residual phase noise voltage of the frequency phase comparator.
As a result, the phase noise characteristics deteriorate.

In this way, when designing a conventional frequency synthesizer, the lowest frequency that can be realized is determined by the phase noise characteristics that are distorted in the device output signal, and the phase noise characteristics and oscillation frequency during self-oscillation of the voltage controlled oscillator. The variable step is determined,
The reference signal generator output frequency is determined from this K, and it has not been possible to realize a frequency synthesizer with smaller variable steps.

The present invention eliminates the drawback that the minimum frequency variable step is limited by the required phase noise characteristics of the conventional device as described above, and provides a frequency with good phase noise characteristics that allows setting an arbitrary minimum frequency variable step. The purpose is to provide a synthesizer.

In the present invention, the output signal of a voltage controlled oscillator is frequency-downgraded by a block diagram puller divider, and is supplied to a frequency phase comparator together with the output signal of a reference signal generator, and the output signal obtained by comparing the
The error signal is negatively fed back to the frequency control terminal of the voltage controlled oscillator via a loop filter that determines the loop characteristics.
In a frequency synthesizer that controls, stabilizes, and sends out the output frequency of a voltage-controlled phase shifter, a DA converter is used to shift the phase of the output signal of the reference signal generator or the input signal or output signal of the glogram pull IR'a. A voltage-controlled phase shifter controlled by a digital signal is inserted through the logic circuit, and a logic circuit calculates the frequency of a single signal generator or programmable frequency divider based on the phase shift amount of the voltage-controlled phase shifter and the count value of the programmable frequency divider. The present invention is characterized in that it is controlled in synchronization with the output signal period and realizes a minimum frequency variable step smaller than the output frequency of the reference signal generator while maintaining good phase noise characteristics.

The frequency synthesizer according to the present invention will be explained in more detail below with reference to the drawings.

FIG. 2 is a block diagram of a frequency synthesizer according to an embodiment of the present invention. The power supply device branches the output signal of the voltage controlled oscillator 1 into two, uses one as the device output OUT, and supplies the other to the programmable frequency divider 2.

Here, the signal is frequency-downgraded and applied to one input of the n-frequency phase comparator 3. The output signal of the reference signal generator 4 is supplied to the other input of the frequency phase comparator 3 via a voltage controlled phase shifter 11, and the frequencies and phases of both components are compared. The obtained differential signal is negatively fed back to the frequency control terminal of the voltage controlled oscillator 10 via the loop filter 5. Further, the count value of the programmable frequency divider 2 and the phase shift amount of the voltage-controlled phase shifter 11 are configured to be controlled by the output data of the logic circuit 13. The DA converter 12 converts the output of the logic circuit 13 into an analog signal and supplies it to the voltage controlled phase shifter 11 .

Now, the required output frequency is f. , reference signal generator fractional part t
p, and the decimal part p is further expressed as a fraction by the number of effective digits according to the desired frequency aperture, and expressed as -8-(0≦a (M%a%M are both positive integers).

Furthermore, the count value of the programmable frequency divider 2 is divided by the number of times M
The logic circuit 13 is set to control in synchronization with the output clock cycle of the reference signal generator so that n+1 is counted during the IL cycle and n is counted during the M-a cycle. At this time, M
The total number counted during division is a(n+1)+(M-a)n=a+Mn-12)
The average count value of the branching cycle of jlgl is N =
n+−・・・・・・・・・(3). This (5)
From the equation, it can be seen that if Mi is large, a frequency synthesizer with a small frequency step can be constructed. However, as it is, the total count value in M division cycles only becomes the required value, and the programmable frequency divider output terminal The periods of the signals that appear in the signals are different. Therefore, at the output terminal of the frequency phase comparator 3, in addition to the output signal component R of the reference signal generator 64, all or part of 7fR (0<b<M%b is a positive integer) is a. appears according to the value of n.

This phase modulates the phase of the output signal of the voltage controlled oscillator l, resulting in deterioration of the phase noise characteristics.

In order to eliminate this, the phase shifter 11 that changes the output signal phase of the reference signal generator 4 in accordance with the frequency division number of the programmable frequency divider is controlled, and the fR component appearing in the output of the frequency phase comparison to eliminate or attenuate. That is, the period in which the voltage-controlled phase shifter 11Fi programmable branching unit counts n + 1 is φ=-2L"L×2π (4)
When n is counted by Mn + a, the logic circuit controls so that each phase n changes relative to the phase of the previous reference signal.

A specific example will be shown to further facilitate understanding. 180MHz
As an example of the configuration of a frequency synthesizer with a minimum weekly wave number variable step of 2.5 kHz, n=1000
0, n=4, the count value N of the programmable frequency divider 2 for each frequency division and the required phase deviation amount φ (rad) of the voltage controlled phase shifter 11
are shown in Table 1.

In Table 1, that is, equation (3) above, by substituting n=10000 and M==4, we get n=-10000+... (6)
becomes. Now, when a=0, N=10000 f, =100 MHz, so from equation (1) above, the output frequency fR of the reference signal generator 4 is. At this time, a 10 kHz clock signal is sent to the output of the voltage controlled phase shifter 11 in FIG. 10000 φ=0 is set, and there is no change regardless of the number of frequency dividers.

Next, when 100.0025 MHz is set as the frequency, a=f, and from the above equation (2), N=10001, and from the above equation (3), the voltage control phase shift is 2πx3 φ = -□ 401)01. The phase shifter 11 is controlled to shift the phase. In the next frequency divider, the amount of phase shift is φ=-V or -0001. When , the branch ratio N = 10000.

In the next frequency divider, the phase shift amount is controlled to φ=--ヱL-10001, and in the next frequency divider, the phase shift amount converges to zero.

When the frequency is set to 10[LOO50MHgK, the turtle value is 2. Also, the frequency is 10 [LOO75M
When Hz K is set, the value of a is 3. In these cases as well, the amount of phase shift changes and converges for each branch.

In this way, the output frequency of the reference signal generator 4 is 10k)
Ig, with a minimum frequency variable step of 2.5 kHz.

In the actual device, the logic circuit 13 is the voltage controlled phase shifter 1
The formula for calculating the required phase shift lid in step 1 becomes complicated.

Further, although various circuit configurations of the voltage-controlled phase shifter 11 can be considered, since there is generally no proportional relationship between the voltage and the amount of phase shift, correction calculations are required when calculating the voltage that provides the required phase shift. Considering these circumstances, the logic circuit 13
For 1C, it is suitable to use a circuit having calculation capabilities such as a microcomputer.

In the above example, the voltage-controlled phase shifter is provided at the output terminal of all reference Ig generators, but the phase comparison reference signal is generally created by frequency-downgrading the output signal of a higher frequency oscillator. Since there are many Even if it is installed anywhere, such as between the stages of the downcomer, it is possible to eliminate or attenuate the fR component from the frequency phase comparator output.

In addition, in the above example, an example was shown in which the count values of the programmer full branching unit were controlled to n and n+1, but in general, n and ntc
(c<n, c is a positive integer) can also be expected to produce the same effect in principle.

Furthermore, although it has been described that the logic circuit 13 controls the programmable frequency divider and the voltage controlled attenuator according to the output signal period of the reference signal generator, it is configured to control both in synchronization with the output signal period of the programmable frequency divider. It is also possible.

As described above, the frequency synthesizer according to the present invention maintains good phase noise characteristics by setting the output frequency of the reference signal generator to a relatively large value. Moreover, it is possible to provide a minimum frequency variation step smaller than the output frequency of the reference signal generator. Since the frequency softness measured over a measurement time longer than the output signal period of the reference signal generator closely matches the frequency softness of the reference signal generator, a high-performance frequency synthesizer can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional indirect control frequency synthesizer. Figure 2 shows the block configuration (2) of a frequency synthesizer according to an embodiment of the present invention. l... Voltage controlled oscillator, 2... Programmable branching unit, 3... Frequency phase comparator, 4... Reference signal generator, 5... Loop filter, 11... Voltage controlled phase shifter , 12... DA converter, 13... logic circuit. Patent Applicant Representative Patent Attorney Nao Ide Filial Procedures Amendment Showa, RG/February l "Japan Patent Office Superior Officer Haruki Shimada 1, Indication of Case 1982 Patent Application No. 114765 2 Title of Invention Half 8n column'!Useful scale 3. Relationship with the case of the person making the amendment Patent applicant 4. Agent 5. Date of amendment order (voluntary amendment) 6. Number of inventions to be increased by amendment (1) In the 6th line of page 3 of the specification, "output frequency fH in minimum variable step" is corrected to "output frequency f, in minimum variable step of output frequency rH of reference signal generator 4." (2) On page 5, line 18 of the specification, "DA converter for shifting the phase" is corrected to "DA converter for shifting the phase".

Claims (1)

[Claims] (Re) A voltage controlled oscillator, a programmable divider that takes the output of this oscillator as input, a reference signal generator, and a frequency phase that has the output of this reference signal generator and the output of the programmable divider as two inputs. In a phase-locked frequency synthesizer that includes a comparator and a loop filter that takes the output of the comparator as an input and provides an output to the control input of the voltage controlled oscillator, the relative phase of the two inputs of the upper fi1m number phase comparator is changed. and a logic circuit that controls the voltage controlled phase shifter and the programmable period divider in synchronization with the output of the reference signal generator or the output of the programmable period divider. A phase-locked frequency synthesizer.