JPH11150475A - Synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a PLL frequency synthesizer which is superior in frequency stability as well as low priced. SOLUTION: Two kinds of reference lock generators and counters for PLL operation systems are prepared. That is, a reference clock generator 101 section having a highly stable frequency characteristics, a counter 103 counting the reference clock, an auxiliary clock generator 102 with frequency stability lower than that of the reference clock generator and providing an output with a higher frequency, and a counter 104 that counts auxiliary clocks. Thus, in parallel with the PLL operation by the reference clock generator 101, the auxiliary PLL operation is conducted in auxiliary manner by clock generator 102.

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a frequency synthesizer, and more particularly, to a frequency synthesizer having a PLL circuit.

2. Description of the Related Art Conventionally, a PLL type synthesizer as shown in FIG. 3 has been used as a reference frequency oscillator in a digital communication network. As shown in FIG.
The L-type synthesizer includes a reference clock generator (1), a counter (2), adders (3) and (5), a multiplier (4), D
A / A converter (6) and a CR oscillator (7). The reference clock generator (1) generates a predetermined reference clock signal and inputs the signal to a counter. The counter (2) supplies a reference clock from a clock terminal to C (described later).
The output of the R oscillator (7) is input from the gate terminal, and the number of reference clocks input while the gate input is at the high level is counted and output. The adder (3) receives the counter output and a standard count value supplied from the outside, and outputs a difference signal between them.
A multiplier (4) multiplies the difference signal by K and inputs the same to an adder (5). The adder (5) adds the K-multiplied difference signal to a standard D / A value supplied from the outside and outputs the result. I do. This output is converted into an analog voltage value by the D / A converter (6) and input to the CR oscillator (7). CR oscillator (7)
Is a voltage-controlled oscillator using a CR oscillation circuit that oscillates at a frequency controlled based on the output voltage of the D / A converter (6). The oscillator generates an output clock and transmits it to the gate of the counter (2). Feedback to terminal. With such a loop configuration, a required clock output can be obtained after a certain period of time. Incidentally, the standard count number and the standard D / A value are uniquely determined by the frequency of the output clock. A TCXO (Temperature Compensated Crystal Oscillator), which is highly stable against temperature and aging, is used as a reference clock oscillator used in the PLL type synthesizer having such a configuration, and its oscillation frequency has a high Q value of the oscillator. It was around 5 MHz. In addition, CR oscillator (7)
Has used a VF converter composed of a resistor element and a capacitor having a wide oscillation frequency dynamic range. Here, a case is considered in which the dynamic range of the output frequency of the CR oscillator (7) needs to be in the range of 10 kHz to 1 MHz, and the output frequency of the reference clock generator TCXO is 5 MHz. When the output frequency of the CR oscillator (7) is the lowest 10 kHz,
This signal is input to the gate terminal of the counter (2) and becomes high level during 50 × 10 ^-6 seconds, and the counter (2)
Counts 250 reference clocks. From such a state, the PLL circuit controls the output frequency of the CR oscillator only when the oscillation frequency of the CR oscillator changes so that the count number becomes at least 251 or 249. The variation of the output frequency of the CR oscillator when this count number changes by one is about 40.
Hz, the error range of the output frequency of the synthesizer is about ± 0.4%.

However, when the output frequency of the CR oscillator (7) is 1 MHz, which is the highest, this signal is input to the gate terminal of the counter (2) and becomes a high level.
The number of reference clocks counted by the counter (2) during × 10 ^-6 seconds is only two.
Even if the frequency of the CR oscillator (7) changes from such a state, if the counted number does not become 3 or 1, C
The output frequency of the R oscillator (7) cannot be controlled, and the amount of change in the output frequency of the CR oscillator when this count changes by one is about 166.7 kHz, and the error range of the output frequency of the synthesizer is ± 16. 67%. That is, when the oscillation frequency of the CR oscillator is high, the PLL synthesizer as shown in FIG. 3 has a drawback that the output frequency cannot be controlled with high accuracy. To compensate for this disadvantage, FIG.
As shown in (1), a frequency divider (8) is inserted between the CR oscillator (7) and the counter (2), and when the frequency of the CR oscillator is high, the frequency division ratio of the frequency division is increased to increase the counter (2). ), There is a method of extending the count time and increasing the number of counts to ensure accuracy. For example, if the oscillation frequency is 1M
In the case of Hz, if the frequency divider (8) is divided by 1/100,
The time when the gate terminal of the counter (2) is at the high level is 50 × 10 ⁻⁶ seconds, and the number of TCXO clocks counted by the counter (2) is 250. At this time,
The oscillation frequency of the CR oscillator when the count number becomes 251 is 0.996 MHz, and the error of the oscillation frequency is ±
0.4%, and the frequency stability of the output clock is improved as compared with the case of FIG.

[0003]

[Problems to be solved by the present invention] However, FIG.
As shown in FIG. 3, the control interval of the conventional PLL shown in FIGS. 3 and 4 depends on the counting time of the counter (2), and the CR oscillator (7) is controlled at this interval. There is a disadvantage that the rapid frequency change of (7) cannot be controlled. For example, when the oscillation frequency (201) of the CR oscillator (7) has a characteristic that fluctuates with time as shown by a dotted line in FIG.
The circuit has a gate input (20) of the count of the counter (2).
Since 3) controls the CR oscillator (7) based on the count value during the high level, the fluctuation (9) of the oscillation frequency of the CR oscillator becomes as shown by the solid line in FIG. As a means for solving such a problem, it is conceivable to use a reference clock generator (1) having a high frequency output. That is, the output clock frequency overall of the synthesizer is a frequency f _0, was counter (2) until the count time frequency variations in the inability to suppress a problem of. However, the reference clock generator (1) needs to have a high frequency stability. Further, in addition to this characteristic, a high-frequency output reference clock generator becomes expensive, and cost reduction is required in all parts. We cannot respond to today's demands. The present invention has been made to solve the above-described problem, and has as its object to provide a PLL-type synthesizer excellent in frequency stability of an output clock at low cost.

[0004]

According to a first aspect of the present invention, there is provided a synthesizer for generating a desired frequency by performing a PLL operation based on a reference clock. The PLL operation is performed in parallel with the reference clock by using an auxiliary clock having an output frequency higher than that of the reference clock in addition to the reference clock.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on illustrated embodiments. FIG. 1 shows a P according to the invention.
FIG. 2 is a block diagram showing an embodiment of an LL type synthesizer, and its configuration and operation are as follows. P shown in FIG.
The LL type synthesizer includes a reference clock generator (101),
Auxiliary clock generator (102), counter (103, 1
04), adders (105, 107, 108, 110),
Multipliers (106, 109), D / A converter (11
1), a CR oscillator (112), and a frequency divider (113). The reference clock generator (101) having a high stable output frequency is used to generate a predetermined reference clock signal, which is input to the clock terminal of the counter (103). To the counter (103), in addition to the reference clock signal, an output signal of a frequency divider (113), which will be described later, is input from a gate terminal, and the number of reference clocks input while the gate input is at a high level is counted. Output this. The adder (105) operates the counter (10
The output of 3) and a reference count value supplied from the outside are input, and these difference signals are output. Multiplier (106)
Multiplies this difference signal by K1 and inputs it to the adder (107). The adder (107) adds the difference signal multiplied by K1 and an output signal of a multiplier (109) described later and outputs the result.
An adder (110) adds the output of the adder (107) and a standard D / A value supplied from the outside and outputs the result. This output is converted into an analog voltage value by the D / A converter (111) and input to the CR oscillator (112).
The CR oscillator (112) oscillates at a frequency controlled based on the output voltage of the D / A converter (111) and generates an output clock. Further, the frequency divider (113) divides the output clock and feeds it back to the gate terminal of the counter (103). On the other hand, the auxiliary clock generator (102) generates a predetermined reference clock signal,
This is input to the clock input terminal of the counter (104). Further, the counter (104) has the CR oscillator (1).
The output frequency of 12) is input from the gate terminal, whereby the counter (104) counts the number of auxiliary clocks input while the gate input is at the high level, and outputs this. The adder (108) operates the counter (1
04) and a standard count value supplied from the outside, and a difference signal between them is output. The multiplier (1
09) is such that the difference signal is multiplied by K2 and input to the adder (107).

Here, it is assumed that the required dynamic range of the output frequency of the CR oscillator is in the range of 10 KHz to 1 MHz, and that the reference clock generator (101)
For example, a high frequency stability device such as TCXO is used, and its output frequency is assumed to be 5 MHz. On the other hand, in this case, if the auxiliary frequency output from the auxiliary clock generator is 200 MHz using a crystal oscillator or the like, the frequency stability at this time is sufficiently less than ± 5000 ppm. Further, the frequency divider (113) performs 1/100 frequency division.
First, the output frequency of the CR oscillator (112) is 10 kHz.
Think about when. The frequency divider (113) divides the frequency of the output signal of the CR oscillator (112) to 100 Hz and outputs it. The divided output signal is supplied to a counter (103).
And the counter (103) outputs 50K reference clocks in 10 × 10 ⁻³ seconds when the output signal is at a high level. The reference clock output from the counter (103) is standardized by an adder (110).
/ A value is added, and the D / A converter (111)
And is converted to an analog signal. The analog signal is input to a CR oscillator, which controls the output frequency of the CR oscillator based on the analog signal.

On the other hand, since a clock signal of 10 KHz is input to the gate terminal of the counter (104), the counter (104) is set to 5 × at which the clock signal becomes high level.
Output 10K auxiliary clocks in 10 ^-5 seconds. The reference clock output from the counter (104) is added to the adder (1).
08) and an adder (107) via a multiplier (109), and are added to a clock signal based on a reference clock signal output from the multiplier (106). The adder (1
07) is added with a standard D / A value by an adder (110), and further added to the D / A converter (11).
The signal is input to 1) and converted into an analog signal. The analog signal is input to a CR oscillator, which controls the output frequency of the CR oscillator based on the analog signal. By repeating this operation many times by the feedback configuration, a required output clock can be obtained after a certain period of time, and the frequency stability when the frequency is controlled is equal to that of the reference clock generator (101) TCXO. Further, the output frequency of the CR oscillator (112) is maintained within the fixed time period for calculating the reference clock number by the counter (103) and even after the fixed time period.
Is controlled based on the auxiliary clock signal output from the controller.

FIG. 2 shows the time variation of the output clock of the PLL based on the above embodiment. The dotted line indicates the frequency stability (201) of only the CR oscillator (112), and the solid line indicates the frequency according to the present invention. It is a frequency stability (202) of a PLL type frequency synthesizer. The operation cycle (203) of the PLL operation by the counter (103) is every 2Tx, and the time for calculating the reference clock number is Tx. The operation cycle (204) of the PLL operation by the counter (104)
Is every 2T, and the time for calculating the number of auxiliary clocks is T. As shown in FIG. 2, the frequency control of the output clock of the PLL of the present invention is performed every 2T, which is shorter than 2Tx, so that the frequency fluctuation is small.

[0009]

As described above, the present invention employs an auxiliary clock having an oscillation frequency higher than that of a reference clock and performs an auxiliary PLL operation in parallel with the PLL operation by the reference clock. The frequency control can be interpolated in a shorter cycle than the frequency control based on the above, and a remarkable effect that a highly stable frequency output can be obtained even if a sudden change occurs in the output of the CR oscillator.

[0010]

[Brief description of the drawings]

FIG. 1 shows an embodiment of a PLL type frequency synthesizer according to the present invention.

FIG. 2 shows how the frequency of the output clock of the PLL-type frequency synthesizer according to the present invention varies.

FIG. 3 shows a configuration of a conventional PLL type synthesizer.

FIG. 4 shows a configuration of a conventional PLL type synthesizer.

FIG. 5 shows a state of a frequency fluctuation of an output clock of a conventional PLL type synthesizer.

[Brief description of reference numerals]

 1, 101 ... reference clock generator 2, 103, 104, 113 ... counter 3, 5, 105, 107, 108, 110 ... adder 4, 106, 109 ... multiplier 6, 111 ... D / A converter 7,112 ... CR oscillator 8,113 ... divided period 102 ... auxiliary clock generator

Claims (1)

[Claims] 1. A synthesizer for generating a desired frequency by performing a PLL operation based on a reference clock, wherein the PLL operation is performed using an auxiliary clock having an output frequency higher than the reference clock in addition to the reference clock. A synthesizer characterized in that the synthesizer is configured to perform processing in parallel with the reference clock. [0001]