JPS59214331A - Pll circuit - Google Patents
Pll circuitInfo
- Publication number
- JPS59214331A JPS59214331A JP58087848A JP8784883A JPS59214331A JP S59214331 A JPS59214331 A JP S59214331A JP 58087848 A JP58087848 A JP 58087848A JP 8784883 A JP8784883 A JP 8784883A JP S59214331 A JPS59214331 A JP S59214331A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frequency
- circuit
- terminal
- oscillation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims abstract description 35
- 238000006243 chemical reaction Methods 0.000 claims 2
- 239000003990 capacitor Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 241000270666 Testudines Species 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
- H03L7/189—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop comprising a D/A converter for generating a coarse tuning voltage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はＰＬＬ回路に係わシ、特にプログラマブルカウ
ンタを帰還路に設けたＰＬＬ回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PLL circuit, and particularly to a PLL circuit in which a programmable counter is provided in a feedback path.
従来、ＰＬＬ回路を発振信号回路として使用するには第
１図に示す如く、端子ｌに基準信号を受け、端子２から
発振信号ｆ を出力する。ＰＬＬ回路には電圧制御発振
器５（以下、ＶＣＯという）が設けである。ＶＣＯ５は
抵抗Ｒ１％可変容量ダイオードＱ１、コンデンサＣ１お
よびコイルＬ１からなる入力回路と発振回路７で構成さ
れている。ロールパスフィルタ４を介してＶＣＯ５の端
子６へ誤差電圧■ｉが入力されると、端子８には誤差電
圧■１に応じた発振信号ｆ。が出力される。誤差電圧Ｖ
ｉの変化電圧ΔＶ、と発振信号ｆ０の変化周波数Δｆ０
との比ｉ ＶＣＯ５の感度という。誤差電圧Ｖ１が第３
図に示すレベル■１〜Ｖ２の範囲で変化すると発振信号
ｆはａ曲線にしたがって周波数ｆ１〜ｆｓの発振周波数
帯域Ｗｍ （ｍは１，２・−・、説明のためｍを４とし
添字の大きいほうが高い周波数・・・ｆ５の帯域とする
）で変化する。端子１から入力される基準信号ｆ１は水
晶発振回路を含む基準周波数発生回路（図示してない）
で生成される。基準周波数発生回路では高い周波数で水
晶発振させ、それを分周して各種の周波数の基準信号ｆ
１を出力するＯ通信用送受機では複数のチャネルに用い
るため所定の周波数ステップの発振信号ｆ。を端子２か
ら出力する。所定の周波数を基準信号ｆｉとし、基準信
号ｆ、のＮ倍（Ｎは整数）の発振信号ｆ。を得るには基
準信号ｆｉと同一の周波数の分周周波ｆ、が得られるよ
うＶＣＯ５の発振イ台号ｆ。を分局すればよい。すなわ
ち、１ ヨ、
発振信号ｆ。を分周比設定回路１０で分周比ＨＫ ｒｙ
定すれたプログラマブルカウンタ９に入力する。Conventionally, in order to use a PLL circuit as an oscillation signal circuit, as shown in FIG. 1, a reference signal is received at a terminal l, and an oscillation signal f is output from a terminal 2. The PLL circuit is provided with a voltage controlled oscillator 5 (hereinafter referred to as VCO). The VCO 5 is composed of an input circuit consisting of a variable capacitance diode Q1 with a resistance R1%, a capacitor C1, and a coil L1, and an oscillation circuit 7. When the error voltage ■i is input to the terminal 6 of the VCO 5 through the roll-pass filter 4, the oscillation signal f corresponding to the error voltage ■1 is input to the terminal 8. is output. error voltage V
The changing voltage ΔV of i and the changing frequency Δf0 of the oscillation signal f0
The ratio i is called the sensitivity of VCO5. The error voltage V1 is the third
When the level shown in the figure changes in the range ■1 to V2, the oscillation signal f follows the a curve and the oscillation frequency band Wm has frequencies f1 to fs (m is 1, 2, etc., for the sake of explanation, m is 4 and the subscript is large. It changes at a higher frequency...the band of f5). The reference signal f1 input from terminal 1 is a reference frequency generation circuit (not shown) including a crystal oscillation circuit.
is generated. The reference frequency generation circuit oscillates a crystal at a high frequency and divides it to generate reference signals f of various frequencies.
In an O communication handset that outputs 1, the oscillation signal f has a predetermined frequency step because it is used for multiple channels. is output from terminal 2. A predetermined frequency is set as a reference signal fi, and an oscillation signal f is N times (N is an integer) the reference signal f. In order to obtain the divided frequency f, which has the same frequency as the reference signal fi, the oscillation number f of the VCO 5 is changed. All you have to do is split it up. That is, 1 yo, oscillation signal f. The frequency division ratio setting circuit 10 sets the frequency division ratio HK ry
input to a predetermined programmable counter 9.
プログラマブルカウンタ９から出力される分周周波ｆ、
と基準信号ｆＪ／は同一周波数となる。分周比設定回路
１０はビン端子Ｄ Ｏｒ Ｄ １・・・（説明のため最
上位ピッ）’（ｒＤ７とする）を有し、ノ９イナリコー
ドで端子Ｄｏ−Ｄ７を「１」またはｒＯＪとする。例え
ば端子ＤＯ〜Ｄ７が’１１１０１０００”ならばＮ−２
３となシ、”１１１０００１１”ガらＮ−１９９となる
。したがって、Ｎ＝２３が設定されるとローパスフィル
り４は第３図に示すレベル■１に近い誤差信号■１をｖ
ｃｏ ５の端子６へ出ノｊする。このときのＶＣＯ５の
ロックされた周波数ｆＬは基準信号ｆ１の２３倍であシ
、周波数ｆｘの直上近傍となっている。周波数ｆＬの発
振信号ｆ。は端子２およびプログラマブルカウンタ９へ
送出される。Ｎ＝１９９に設定されたときは第３図に示
すレベル■２に近い誤差（己号■１をＶＣＯ５の端子６
へ出力する。このときのＶＣＯ５のロックされた周波数
九は基準信号ｆｉの１９９倍であシ、周波数ｆ５の直下
近傍となっている。実際の回路ではそれぞれの回路は集
積回路化されＶＣＯ５の発振回路７ｕ外伺はコンデンサ
により自走周波数を数１０ ＭＨｚ〜１ ｋＨｚ程闇の
範囲で変更出来るようになっている。自走周波数が数１
０ ＭＥ（ｚと高い場合はプログラマブルカウンタ９と
端子２との間に混合器を設け、プログラマブルカウンタ
９から出力される分周周波ｆｄと基準信号ｆ、の周波数
が一致するようなローカル周波数を加える。なお、プロ
グ２マプルカウンタ９を帰還路に設けたＰＬＬ回路には
他に各種回路がある。The divided frequency f output from the programmable counter 9,
and reference signal fJ/ have the same frequency. The frequency division ratio setting circuit 10 has a bin terminal D Or D 1... (for the sake of explanation, the highest pitch)' (rD7), and the terminal Do-D7 can be set to "1" or rOJ with the No9 binary code. do. For example, if terminals DO~D7 are '11101000', then N-2
3, "11100011" becomes N-199. Therefore, when N=23 is set, the low-pass filter 4 converts the error signal ■1 close to the level ■1 shown in FIG.
output to terminal 6 of co 5. At this time, the locked frequency fL of the VCO 5 is 23 times the reference signal f1, and is close to just above the frequency fx. Oscillation signal f with frequency fL. is sent to terminal 2 and programmable counter 9. When N=199 is set, an error close to level ■2 shown in Figure 3 (self-signal ■1 is set to terminal 6 of VCO5).
Output to. At this time, the locked frequency 9 of the VCO 5 is 199 times the reference signal fi, which is just below the frequency f5. In the actual circuit, each circuit is integrated, and the free-running frequency of the oscillation circuit 7u of the VCO 5 can be varied within a range of several tens of MHz to 1 kHz using a capacitor. Free running frequency is several 1
0 ME (If z is high, a mixer is provided between the programmable counter 9 and the terminal 2, and a local frequency is added so that the frequency of the divided frequency fd output from the programmable counter 9 and the reference signal f match. Note that there are various other PLL circuits in which the program 2 mapple counter 9 is provided in the return path.
ＰＬＬ回路の位相比較器３、ローフ４スフイルタ４、Ｖ
ＣＯ５、プログラマブルカウンタ９等に係わる各部要素
および回路は各部の雑音指数、相互の干渉、温度および
電源変動によるドリフト、動作特性等によジ取扱う信号
に対し、付加的な雑音を発生する。特にＶＣＯ５では、
自走周波数が誤差信号Ｖ。PLL circuit phase comparator 3, loaf 4 filter 4, V
Each element and circuit related to the CO5, programmable counter 9, etc. generates additional noise to the signal being handled due to the noise figure of each part, mutual interference, drift due to temperature and power supply fluctuations, operating characteristics, etc. Especially in VCO5,
The free running frequency is the error signal V.
の変化電圧Δ■、によ）ロックされるので発振信号ｆｏ
の変化周波数Δｆ は非周期性、非対称性をもつことに
な）キャリヤ・ノイズ比（以下、Ｃ／Ｎと記す）が悪化
する。ＣＡを改善するにはＶＣＯ５の変化電圧Δｖ１に
対する変化周波数Δｆｏを少なくすること、すなわち、
ＶＣＯ５の感度を下げればよい。The oscillation signal fo is locked by the changing voltage Δ■,
The change frequency Δf has non-periodic and asymmetric properties, which deteriorates the carrier-to-noise ratio (hereinafter referred to as C/N). To improve CA, reduce the change frequency Δfo with respect to the change voltage Δv1 of the VCO 5, that is,
All you have to do is lower the sensitivity of VCO5.
しかし、ＶＣＯ５の感度を下げると発振周波数帯域が狭
くなシ、数１００チヤネルにもおよぶトランシーバ等の
発振信号ｆ。を生成できない。また、チャネル相互の間
隔、すなわち、基準信号ｆｉの周波数トローノ々スフイ
ルタ４のカットオフ周波数トの間にはスジリアスを減衰
しＣＡを高くするための設計条件およびＰＬＬ回路全般
の動作を定める設計条件があるので位相比較器３、ロー
パスフィルタ４およびＶＣＯ５の各部定数を最適値とし
てもＣ／Ｈの大巾な改善ができない。このため、複数の
ＰＬＬ回路を組合せた回路、ｖＣＯ５内部に切換器を設
ける回路等によ少対処する方法が提案されているが十分
ではない。However, if the sensitivity of the VCO 5 is lowered, the oscillation frequency band becomes narrower, and the oscillation signal f of a transceiver, etc., which spans several hundred channels. cannot be generated. In addition, there are design conditions for attenuating streaks and increasing CA and design conditions for determining the overall operation of the PLL circuit between the channels, that is, the cutoff frequency of the frequency tonoise filter 4 of the reference signal fi. Therefore, even if the constants of each part of the phase comparator 3, low-pass filter 4, and VCO 5 are set to optimum values, the C/H cannot be significantly improved. For this reason, methods have been proposed to address this issue, such as a circuit that combines a plurality of PLL circuits, a circuit that includes a switch inside the vCO5, etc., but these methods are not sufficient.
本発明は上述した点にかんがみなされたもので、通信用
送受機等、多数のチャネルに適用する発振信号を生成し
、キャリヤ・ノイズ比を改善したＰＬＬ回路を提供する
ことを目的とする。The present invention has been made in view of the above points, and an object of the present invention is to provide a PLL circuit that generates oscillation signals to be applied to a large number of channels in communication handsets and the like, and has an improved carrier-to-noise ratio.
本発明は第１の入力回路を有する電圧制御発振器に第２
の入力回路を併設し、更に、プログラマブルカウンタの
上位桁をアナログ量に変換して、このアナログ量を第２
の入力回路へ加える。The present invention provides a voltage controlled oscillator having a first input circuit with a second input circuit.
It also has an input circuit that converts the upper digits of the programmable counter into an analog quantity, and converts this analog quantity into a second input circuit.
Add to the input circuit.
プログラマブルカウンタで設定される１つの発振信号は
所属する上位桁の信号（第２の入力回路経由）と自身の
誤差信号（第１の入力回路経由）とによシミ圧制御発振
器を制御する構造となっている。One oscillation signal set by the programmable counter has a structure in which the stain pressure control oscillator is controlled by the signal of the upper digit to which it belongs (via the second input circuit) and its own error signal (via the first input circuit). It has become.
以下、本発明にガるＰＬＴ、回路を第２図にしたがって
詳述する。Hereinafter, the PLT and circuit according to the present invention will be described in detail with reference to FIG.
第２図は本発明によるＰＬＬ回路の一実施例におけるブ
ロック図である。FIG. 2 is a block diagram of an embodiment of a PLL circuit according to the present invention.
第２図において１１は電圧制御発振器（ＶＣＯ）、１３
はデジタルアナログ変換器である。ＶＣＯ１１は抵抗Ｒ
２、可変容量ダイオードＱ２およびコンデンサＣ２から
なる第２の入力回路が第１の入力回路に併設されている
。In FIG. 2, 11 is a voltage controlled oscillator (VCO), 13
is a digital to analog converter. VCO11 is resistor R
2. A second input circuit consisting of a variable capacitance diode Q2 and a capacitor C2 is provided alongside the first input circuit.
第２の入力回路は第１の入力回路の端子６に対応して端
子１２を有し、コンデンサＣ２の一端は入力抵抗Ｒ２を
介して端子１２と接続されている。The second input circuit has a terminal 12 corresponding to the terminal 6 of the first input circuit, and one end of the capacitor C2 is connected to the terminal 12 via an input resistor R2.
また、入力抵抗Ｒ２とコンデンサＣ２との接続点と基準
電位点の間には可変容量ダイオードＱ２が設けである。Further, a variable capacitance diode Q2 is provided between the connection point between the input resistor R2 and the capacitor C2 and the reference potential point.
コンデンサＣ２の他端はコンデンサＣ３の他端と共に発
振回路の入力側に接続されている。更に、コンデンサＣ
２とＣ３との接続点と基準電位点の間にはコイルＬ２が
接続されている。The other end of capacitor C2 is connected to the input side of the oscillation circuit together with the other end of capacitor C3. Furthermore, capacitor C
A coil L2 is connected between the connection point between 2 and C3 and the reference potential point.
コンデンサＣ３１Ｃ２およびコイルＬ２の定数は端子６
へ入力される誤差信号■１と端子１２へ入力される桁信
号ｖＫに応じて第３図のｂ１曲線、 ｂ２曲紗・・・が
得られるよう設定する。The constants of capacitor C31C2 and coil L2 are at terminal 6.
The settings are made so that the b1 curve, b2 curve, etc. shown in FIG.
デジタルアナログ変換器１３の入力側は分周比設定回路
１０の上位桁のビン端子Ｄ６およびＤ７と接続されバイ
ナリモードでデジタル量を入力される。この例における
デジタル量は００”０１＃°′１０”１１”でアシ、デ
ジタルアナログ変換器１３はこのデジタル量をアナログ
量に変換して桁信号ＶＫとしてＶＣＯ１１の端子１２へ
出力する。第１〜第４の桁信号ｖＫは第３図に示す第１
の発振周波数帯域Ｗｌ第２の発振周波数帯域Ｗ２・・・
に対応している。The input side of the digital-to-analog converter 13 is connected to the higher-order bin terminals D6 and D7 of the frequency division ratio setting circuit 10, and receives a digital amount in binary mode. In this example, the digital quantity is 00"01#°'10"11", and the digital-to-analog converter 13 converts this digital quantity into an analog quantity and outputs it to the terminal 12 of the VCO 11 as a digit signal VK. The fourth digit signal vK is the first digit signal vK shown in FIG.
oscillation frequency band Wl second oscillation frequency band W2...
It corresponds to
ここで、分局比較回路１０でピン端子Ｄｏ％Ｄ７が”
１１１０１０００ ″すなわち、Ｎ＝２３に設定される
と端子６へは従来と同様な誤差信号ｖｉが加えられる。Here, in the branch comparison circuit 10, the pin terminal Do%D7 is "
11101000'', that is, when N=23, an error signal vi similar to the conventional one is applied to the terminal 6.
端子１２へ桁信号ｖＫが送出されない従来例では２曲線
のｐ、点に相当する誤差信号Ｖ、 （コンデンサＣ２が
０３と替っているので若干動作曲線が異なる）に対応し
た周波数ｆＬの発振信号ｆ０がロックされる。本発明で
は桁信号ＶＫが送出されているのでｂ１曲線上の２２点
でロックする。In the conventional example in which the digit signal vK is not sent to the terminal 12, an oscillation signal with a frequency fL corresponding to the error signal V corresponding to the point p and point of the two curves (the operating curve is slightly different because the capacitor C2 is replaced with 03) is generated. f0 is locked. In the present invention, since the digit signal VK is sent out, it is locked at 22 points on the b1 curve.
周波数ｆＬは２２点を中心としてｂ１曲線上で微少変動
するが変動中は少なくなシ、キャリヤ・ノイズ比は改善
される。Although the frequency fL slightly fluctuates on the b1 curve around the 22nd point, the frequency is small during the fluctuation, and the carrier-to-noise ratio is improved.
上記実施例ではデジタルアナログ変換器１３の入力側を
バイナリモードによるデジタル量としたがこれに限定さ
れない。また、入力側への上位桁の数および情報伝達方
法も実施例に限定されない。In the above embodiment, the input side of the digital-to-analog converter 13 is a digital quantity in binary mode, but the invention is not limited to this. Furthermore, the number of upper digits and the method of transmitting information to the input side are not limited to the embodiments.
更に、分周比設定回路１０はマイクロコンピー−タ等で
代替してもよい。Furthermore, the frequency division ratio setting circuit 10 may be replaced by a microcomputer or the like.
本発明によるＰＬＬ回路は第１の入力回路に併設された
第２の入力回路を有する電圧制御発振器と、電圧制御発
振器の分割された発振周波数帯域に対応したプログラマ
ブルカウンタの上位桁をアナログ量に変換するデジタル
アナログ変換器とを具備した構成としであるため、第２
の入力回路への信号がアナログ量であるところに特徴を
有している。The PLL circuit according to the present invention includes a voltage controlled oscillator having a second input circuit attached to a first input circuit, and converts the upper digits of a programmable counter corresponding to the divided oscillation frequency band of the voltage controlled oscillator into an analog quantity. Since the configuration is equipped with a digital-to-analog converter, the second
The feature is that the signal to the input circuit is an analog quantity.
このため、プログラマブルカウンタの上位桁と電圧制御
発振器の分割された発振周波数帯域との対応を自由に定
められ、利用可能な発振周波数帯域中を狭くすることな
くキャリヤ・ノイズ比を改善できる効果がある。Therefore, the correspondence between the upper digits of the programmable counter and the divided oscillation frequency bands of the voltage controlled oscillator can be freely determined, which has the effect of improving the carrier-to-noise ratio without narrowing the available oscillation frequency band. .
第１図は従来のＰＬＬ回路、第２図は本発明の一実施例
を示すＰＬＬ回路のブロック図、第３図は第１図および
第２図の電圧制御発振器の動作特性を示すグラフである
。図中符号１，２は端子、３は位相比較器、４はローパ
スフィルタ、５．１１は電圧制御発振器、７は発振回路
、９はプログラマブルカウンタ、１０は分周比設定回路
、Ｃ１ｌｃ２１Ｃ３はコンデンサ、Ｌ １ ＋ Ｌ
２はコイル、Ｒ１。
Ｒ２＋Ｒ３は抵抗、Ｑｔ 、Ｑｚは可変容量ダイオー
ドである。
特許出願人 八重洲無線株式会社
第１図
５
亀２図
１FIG. 1 is a conventional PLL circuit, FIG. 2 is a block diagram of a PLL circuit showing an embodiment of the present invention, and FIG. 3 is a graph showing operating characteristics of the voltage controlled oscillator shown in FIGS. 1 and 2. . In the figure, symbols 1 and 2 are terminals, 3 is a phase comparator, 4 is a low-pass filter, 5.11 is a voltage controlled oscillator, 7 is an oscillation circuit, 9 is a programmable counter, 10 is a frequency division ratio setting circuit, C1lc21C3 is a capacitor, L 1 + L
2 is the coil, R1. R2+R3 are resistors, and Qt and Qz are variable capacitance diodes. Patent applicant Yaesu Musen Co., Ltd. Figure 1 5 Turtle 2 Figure 1
Claims (1)
波数帯域で発振する電圧制御発振器と、プログラマブル
カウンタとを有するＰＬＬ回路において、入力される信
号のレベルに応じて前記所定の発信周波数帯域を分割す
べく前記第１の入力回路に併設された第２の入力回路と
、前記分割された複数の発振周波数帯域に対応した前記
プログラマブルカウンタの上位桁をアナログ量に変換す
るデジタルアナログ変換手段とを具備し、前記デジタル
アナログ変換手段で得た前記信号を前記第２の入力回路
へ出力し、分割された発振周波数帯域ごとに前記誤差信
号に応じてロックするよう構成したことを特徴とするＰ
ＬＬ回路。In a PLL circuit that includes a voltage controlled oscillator that receives an error signal from a first input circuit and oscillates in a predetermined oscillation frequency band, and a programmable counter, the predetermined oscillation frequency band is adjusted according to the level of the input signal. a second input circuit attached to the first input circuit for dividing, and digital-to-analog conversion means for converting the upper digits of the programmable counter corresponding to the plurality of divided oscillation frequency bands into analog quantities. P characterized in that the signal obtained by the digital-to-analog conversion means is output to the second input circuit and locked in accordance with the error signal for each divided oscillation frequency band.
LL circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58087848A JPS59214331A (en) | 1983-05-19 | 1983-05-19 | Pll circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58087848A JPS59214331A (en) | 1983-05-19 | 1983-05-19 | Pll circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59214331A true JPS59214331A (en) | 1984-12-04 |
Family
ID=13926304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58087848A Pending JPS59214331A (en) | 1983-05-19 | 1983-05-19 | Pll circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59214331A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56164633A (en) * | 1980-05-21 | 1981-12-17 | Toshiba Corp | Frequency synthesizer |
| JPS57160227A (en) * | 1981-03-30 | 1982-10-02 | Fujitsu Ltd | Frequency synthesizer |
-
1983
- 1983-05-19 JP JP58087848A patent/JPS59214331A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56164633A (en) * | 1980-05-21 | 1981-12-17 | Toshiba Corp | Frequency synthesizer |
| JPS57160227A (en) * | 1981-03-30 | 1982-10-02 | Fujitsu Ltd | Frequency synthesizer |
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