JPS5917870U - Flat semiconductor package test substrate - Google Patents
Flat semiconductor package test substrateInfo
- Publication number
- JPS5917870U JPS5917870U JP11248182U JP11248182U JPS5917870U JP S5917870 U JPS5917870 U JP S5917870U JP 11248182 U JP11248182 U JP 11248182U JP 11248182 U JP11248182 U JP 11248182U JP S5917870 U JPS5917870 U JP S5917870U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- test substrate
- package test
- flat semiconductor
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は、従来のフラットパッケージ型半導素子試験用
ソケットの側面図であり、第2図イ9口は、この考案の
フラットパッケージ型半導体素子試験用基板を例示する
ための一部拡大断面図、第3図は第2図に対応ずや主要
部の平面図である。
1.1′・・・絶縁基板、2・・・銅箔回路、2′・・
・端子部、3・・・フラットパッケージ、4・・・テー
パ、5・・・固定板、6・・・固定枠、7・・・耐熱性
ゴムシート、8・・・突起、9・・・穴。
補正 昭58. 8.23
考案の名称を次のように補正する。
■フラット型半導体パッケージ試験用基板実用新案登録
請求の範囲を次のように補正する。
O実用新案登録請求の範囲
電気回路を形成したプリント配線板の所定位置に、フラ
ット型半導体パッケージのコーナ部もしくは辺部の2力
所以上で位置決めするための固定板を有する固定枠を取
り付けたことを特徴とするフラット型半導体パッケージ
試験用基板。
図面の簡単な説明を次のように補正する。
明細書第6頁第5〜6行目および第7〜8行目の「型半
導体素子」を削除します。FIG. 1 is a side view of a conventional flat package type semiconductor device testing socket, and FIG. 3, which corresponds to FIG. 2, are plan views of the main parts. 1.1'...Insulating board, 2...Copper foil circuit, 2'...
・Terminal part, 3...Flat package, 4...Taper, 5...Fixing plate, 6...Fixing frame, 7...Heat-resistant rubber sheet, 8...Protrusion, 9... hole. Amended 1984. 8.23 The title of the invention shall be amended as follows. ■The scope of the claim for utility model registration of flat type semiconductor package test substrate shall be amended as follows. O Utility Model Registration Scope of Claims A fixing frame having fixing plates for positioning at two or more force points on the corner or side of a flat semiconductor package is attached to a predetermined position of a printed wiring board on which an electric circuit is formed. A flat semiconductor package test board featuring: The brief description of the drawing has been amended as follows. Delete "type semiconductor device" from lines 5 to 6 and lines 7 to 8 of page 6 of the specification.
Claims (1)
ットパッケージ型半導体素子のコーナ部もしくは辺部の
2力所以上で位置決めするための固定板を有する固定枠
を取り付けたことを特徴とするフラットパッケージ型半
導体素子試験用基板。A flat package characterized in that a fixing frame having a fixing plate for positioning a flat package type semiconductor element at two or more force points at a corner or a side is attached to a predetermined position of a printed wiring board on which an electric circuit is formed. Substrate for testing type semiconductor devices.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11248182U JPS5917870U (en) | 1982-07-24 | 1982-07-24 | Flat semiconductor package test substrate |
US06/875,517 US4766371A (en) | 1982-07-24 | 1986-06-19 | Test board for semiconductor packages |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11248182U JPS5917870U (en) | 1982-07-24 | 1982-07-24 | Flat semiconductor package test substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5917870U true JPS5917870U (en) | 1984-02-03 |
JPH0120701Y2 JPH0120701Y2 (en) | 1989-06-21 |
Family
ID=30260740
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11248182U Granted JPS5917870U (en) | 1982-07-24 | 1982-07-24 | Flat semiconductor package test substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5917870U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6156580U (en) * | 1984-09-17 | 1986-04-16 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53160369U (en) * | 1977-05-23 | 1978-12-15 | ||
JPS5467672A (en) * | 1977-11-09 | 1979-05-31 | Hitachi Ltd | Jig of inspecting characteristic of electronic parts |
JPS55146938A (en) * | 1979-05-02 | 1980-11-15 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Aging device for semiconductor element |
JPS58140479U (en) * | 1982-03-16 | 1983-09-21 | 日本電気ホームエレクトロニクス株式会社 | Semiconductor device characteristic measuring device |
-
1982
- 1982-07-24 JP JP11248182U patent/JPS5917870U/en active Granted
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53160369U (en) * | 1977-05-23 | 1978-12-15 | ||
JPS5467672A (en) * | 1977-11-09 | 1979-05-31 | Hitachi Ltd | Jig of inspecting characteristic of electronic parts |
JPS55146938A (en) * | 1979-05-02 | 1980-11-15 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Aging device for semiconductor element |
JPS58140479U (en) * | 1982-03-16 | 1983-09-21 | 日本電気ホームエレクトロニクス株式会社 | Semiconductor device characteristic measuring device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6156580U (en) * | 1984-09-17 | 1986-04-16 |
Also Published As
Publication number | Publication date |
---|---|
JPH0120701Y2 (en) | 1989-06-21 |
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