JPS5952485U - Semiconductor test board - Google Patents
Semiconductor test boardInfo
- Publication number
- JPS5952485U JPS5952485U JP14928282U JP14928282U JPS5952485U JP S5952485 U JPS5952485 U JP S5952485U JP 14928282 U JP14928282 U JP 14928282U JP 14928282 U JP14928282 U JP 14928282U JP S5952485 U JPS5952485 U JP S5952485U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- test board
- semiconductor test
- page
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のソケットを示す斜視図、第２図はこの考
案における基板の構造を模式的に示すための断面図、第
３図および第４図は基板上にフラットパッケージ型半導
体をセットしたときの状態を模式的に例示するための断
面図、第５図イは基板上にミニフラットパッケージ型半
導体をセットしたときの模式的断面図、同口はその模式
的平面図、第６図イ〜ツは固定用爪の形状を模式的に例
示するための斜視図、第７図はこの考案の基板上にフラ
ットパッケージ型半導体をセットしたときの一例を模式
的に示す断面図イおよび平面図口である。
１・・・基板、２・・・電気回路、２′・・・端子、３
・・・スルーホール、４・・・半導体、４′・・・リー
ドピン、５ ・・・・蓋板、５′・・・突起物、６・
・・座ぐり穴、７・・・固定用爪、ａ・・・コーナ部、
ｂ・・・辺部、Ｃ・・・リードピンの間隙部。
補正 昭５８．８．２６
考案の名称を次のように補正する。
■半導体パッケージ試験用基板
実用新案登録請求の範囲を次のように補正する。
■実用新案登録請求の範囲
電気回路を形成したプリント配線基板の所定位置に、半
導体パッケージの正確な位置決めをするための固定用爪
を有し、しかも、半導体パッケージのリード部とプリン
ト配線基板上め端子部とが、ソケット等のコンタクト機
構を介在させないで直接密着する構造であることを特徴
とする半導体パッケージ試験用基板。
図面の簡単な説明を次のように補正する。
明細書第１０頁第１２行の「半導体」を「半導体パッケ
ージ」と補正する。
明細書第１Ｏ頁第１４行の「半導体」を「半導体パッケ
ージ」と補正する。 ′
明細書第１０頁第１８行の「半導体」を「半導体パッケ
ージ」と補正する。
明細書第１１頁第２行の「半導体」を「半導体パッケー
ジ」と補正する。
明細書第１０頁第１２行目、第１０頁第１４行目。
第１０頁第１８行目における「パッケージ」を削除しま
す。Figure 1 is a perspective view showing a conventional socket, Figure 2 is a sectional view schematically showing the structure of the board in this invention, and Figures 3 and 4 show a flat package semiconductor set on the board. Figure 5A is a schematic cross-sectional view when a mini-flat package semiconductor is set on a substrate; -A is a perspective view schematically illustrating the shape of the fixing claw, and FIG. It is the mouth. 1... Board, 2... Electric circuit, 2'... Terminal, 3
...Through hole, 4...Semiconductor, 4'...Lead pin, 5...Lid plate, 5'...Protrusion, 6...
... Counterbore hole, 7... Fixing claw, a... Corner part,
b...Side part, C...Gap part between lead pins. Amendment: August 26, 1982: The name of the invention is amended as follows. ■The scope of the utility model registration claim for semiconductor package testing substrates is amended as follows. ■ Scope of claim for utility model registration The printed wiring board on which the electric circuit is formed has a fixing claw for accurately positioning the semiconductor package at a predetermined position. 1. A semiconductor package testing board, characterized in that the terminal portion is in direct contact with the terminal portion without intervening a contact mechanism such as a socket. The brief description of the drawing has been amended as follows. "Semiconductor" on page 10, line 12 of the specification is corrected to "semiconductor package.""Semiconductor" on page 1, line 14 of the specification is corrected to "semiconductor package."'"Semiconductor" on page 10, line 18 of the specification is corrected to "semiconductor package.""Semiconductor" in the second line of page 11 of the specification is corrected to "semiconductor package." Specification page 10, line 12, page 10, line 14. Delete "Package" on page 10, line 18.
Claims (1)
導体の正確な位置決めをするための固定用爪を有し、し
かも、半導体リード部とプリント配線基板上の端子部と
が、ソケット等のコンタクト機構を介在させないで直接
密着する構造であることを特徴とする半導体試験用基板
。The printed wiring board on which the electric circuit is formed has a fixing claw for accurate positioning of the semiconductor at a predetermined position, and the semiconductor lead part and the terminal part on the printed wiring board are connected to a contact such as a socket. A semiconductor test board characterized by having a structure in which it is directly attached without any intervening mechanism.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14928282U JPS5952485U (en) | 1982-09-29 | 1982-09-29 | Semiconductor test board |
| GB08322587A GB2130383B (en) | 1982-09-14 | 1983-08-23 | Test board for semiconductor packages |
| US06/875,517 US4766371A (en) | 1982-07-24 | 1986-06-19 | Test board for semiconductor packages |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14928282U JPS5952485U (en) | 1982-09-29 | 1982-09-29 | Semiconductor test board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5952485U true JPS5952485U (en) | 1984-04-06 |
Family
ID=30331423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14928282U Pending JPS5952485U (en) | 1982-07-24 | 1982-09-29 | Semiconductor test board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5952485U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60251637A (en) * | 1984-05-29 | 1985-12-12 | Hitachi Electronics Eng Co Ltd | Positioning unit for thin integrated circuit |
-
1982
- 1982-09-29 JP JP14928282U patent/JPS5952485U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60251637A (en) * | 1984-05-29 | 1985-12-12 | Hitachi Electronics Eng Co Ltd | Positioning unit for thin integrated circuit |
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