JPS6052659U - Mounting structure of flat package integrated circuit - Google Patents

Mounting structure of flat package integrated circuit

Info

Publication number
JPS6052659U
JPS6052659U JP14381883U JP14381883U JPS6052659U JP S6052659 U JPS6052659 U JP S6052659U JP 14381883 U JP14381883 U JP 14381883U JP 14381883 U JP14381883 U JP 14381883U JP S6052659 U JPS6052659 U JP S6052659U
Authority
JP
Japan
Prior art keywords
integrated circuit
flat package
package integrated
board
mounting structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14381883U
Other languages
Japanese (ja)
Other versions
JPH0217501Y2 (en
Inventor
竹縄　清次
Original Assignee
富士通テン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通テン株式会社 filed Critical 富士通テン株式会社
Priority to JP14381883U priority Critical patent/JPS6052659U/en
Publication of JPS6052659U publication Critical patent/JPS6052659U/en
Application granted granted Critical
Publication of JPH0217501Y2 publication Critical patent/JPH0217501Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来からのフラットパッケージ集積口”　路の
実装状態を示す斜視図、第２図は本考案の一実施例のフ
ラットパッケージ集積回路の実装状態を示す斜視図であ
る。 ５・・・フラットパッケージ集積回路、６・・・配線、
７・・・サブ基板、８・・・ピン、１０・・・メイン基
板、１１・・・孔、１２・・・プリント配線。Fig. 1 is a perspective view showing the mounting state of a conventional flat package integrated circuit, and Fig. 2 is a perspective view showing the mounting state of a flat package integrated circuit according to an embodiment of the present invention.5... Flat package integrated circuit, 6... wiring,
7... Sub board, 8... Pin, 10... Main board, 11... Hole, 12... Print wiring.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電気的に接続するための複数のピンを有するサブ基板を
設け、そのサブ基板にフラットパッケージ集積回路を接
着し、フラットパッケージ集積回路の配線とサブ基板の
ピンとを接続し、サブ基板のピンをメイン基板のプリン
ト配線の孔にさし込み、はんだ付けして固定することを
特徴とするフラットパッケージ集積回路の実装構造。A sub-board with multiple pins for electrical connection is provided, a flat package integrated circuit is bonded to the sub-board, the wiring of the flat package integrated circuit is connected to the pins of the sub-board, and the pins of the sub-board are connected to the main board. A mounting structure for a flat package integrated circuit characterized by inserting it into a printed wiring hole on a board and fixing it by soldering.
JP14381883U 1983-09-16 1983-09-16 Mounting structure of flat package integrated circuit Granted JPS6052659U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14381883U JPS6052659U (en) 1983-09-16 1983-09-16 Mounting structure of flat package integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14381883U JPS6052659U (en) 1983-09-16 1983-09-16 Mounting structure of flat package integrated circuit

Publications (2)

Publication Number Publication Date
JPS6052659U true JPS6052659U (en) 1985-04-13
JPH0217501Y2 JPH0217501Y2 (en) 1990-05-16

Family

ID=30320908

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14381883U Granted JPS6052659U (en) 1983-09-16 1983-09-16 Mounting structure of flat package integrated circuit

Country Status (1)

Country Link
JP (1) JPS6052659U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5754390A (en) * 1980-08-11 1982-03-31 Rca Corp
JPS57180155A (en) * 1981-04-30 1982-11-06 Nec Corp Vessel for electronic circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5754390A (en) * 1980-08-11 1982-03-31 Rca Corp
JPS57180155A (en) * 1981-04-30 1982-11-06 Nec Corp Vessel for electronic circuit

Also Published As

Publication number Publication date
JPH0217501Y2 (en) 1990-05-16

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