JPS58144846U - Packages for integrated circuits - Google Patents

Packages for integrated circuits

Info

Publication number
JPS58144846U
JPS58144846U JP4043682U JP4043682U JPS58144846U JP S58144846 U JPS58144846 U JP S58144846U JP 4043682 U JP4043682 U JP 4043682U JP 4043682 U JP4043682 U JP 4043682U JP S58144846 U JPS58144846 U JP S58144846U
Authority
JP
Japan
Prior art keywords
integrated circuits
packages
integrated circuit
terminals
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4043682U
Other languages
Japanese (ja)
Inventor
馬場 達夫
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP4043682U priority Critical patent/JPS58144846U/en
Publication of JPS58144846U publication Critical patent/JPS58144846U/en
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来技術による集積回路のプリント基板への
実装状態を示す正面図、第2図は、本考案の一実施例の
正面図である。 1・・・・・・LSIのボディー、2a・・・ピン、2
b・・・ピン、3・・・プリント基板、4・・・挿入穴
FIG. 1 is a front view showing a conventional integrated circuit mounted on a printed circuit board, and FIG. 2 is a front view of an embodiment of the present invention. 1...LSI body, 2a...pin, 2
b...pin, 3...printed circuit board, 4...insertion hole.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 集積回路のボディーの上面と略、平行になるように設け
られた前記集積回路の端子の少なくとも任意の2ケ所の
端子を、前記集積回路を実装する基板に対し略直角方向
に曲げたことを特徴とする集積回路用パッケージ。
At least two arbitrary terminals of the terminals of the integrated circuit, which are provided to be substantially parallel to the upper surface of the body of the integrated circuit, are bent in a direction substantially perpendicular to the substrate on which the integrated circuit is mounted. Package for integrated circuits.
JP4043682U 1982-03-24 1982-03-24 Packages for integrated circuits Pending JPS58144846U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4043682U JPS58144846U (en) 1982-03-24 1982-03-24 Packages for integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4043682U JPS58144846U (en) 1982-03-24 1982-03-24 Packages for integrated circuits

Publications (1)

Publication Number Publication Date
JPS58144846U true JPS58144846U (en) 1983-09-29

Family

ID=30051660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4043682U Pending JPS58144846U (en) 1982-03-24 1982-03-24 Packages for integrated circuits

Country Status (1)

Country Link
JP (1) JPS58144846U (en)

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