JPS59159557A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPS59159557A
JPS59159557A JP58033279A JP3327983A JPS59159557A JP S59159557 A JPS59159557 A JP S59159557A JP 58033279 A JP58033279 A JP 58033279A JP 3327983 A JP3327983 A JP 3327983A JP S59159557 A JPS59159557 A JP S59159557A
Authority
JP
Japan
Prior art keywords
buffer circuit
signal buffer
cells
region
circuit cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58033279A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0465547B2 (enrdf_load_stackoverflow
Inventor
Hidekazu Minami
南　英一
Kiyokazu Arai
新井　喜代和
Tsutomu Sumimoto
勉 住本
Koichi Ikeda
池田　公一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58033279A priority Critical patent/JPS59159557A/ja
Publication of JPS59159557A publication Critical patent/JPS59159557A/ja
Publication of JPH0465547B2 publication Critical patent/JPH0465547B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP58033279A 1983-03-01 1983-03-01 半導体集積回路装置 Granted JPS59159557A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58033279A JPS59159557A (ja) 1983-03-01 1983-03-01 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58033279A JPS59159557A (ja) 1983-03-01 1983-03-01 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPS59159557A true JPS59159557A (ja) 1984-09-10
JPH0465547B2 JPH0465547B2 (enrdf_load_stackoverflow) 1992-10-20

Family

ID=12382085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58033279A Granted JPS59159557A (ja) 1983-03-01 1983-03-01 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS59159557A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59167036A (ja) * 1983-03-14 1984-09-20 Nec Corp 半導体集積回路
US5015600A (en) * 1990-01-25 1991-05-14 Northern Telecom Limited Method for making integrated circuits

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58209158A (ja) * 1982-05-31 1983-12-06 Nec Corp マスタスライス半導体装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58209158A (ja) * 1982-05-31 1983-12-06 Nec Corp マスタスライス半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59167036A (ja) * 1983-03-14 1984-09-20 Nec Corp 半導体集積回路
US5015600A (en) * 1990-01-25 1991-05-14 Northern Telecom Limited Method for making integrated circuits

Also Published As

Publication number Publication date
JPH0465547B2 (enrdf_load_stackoverflow) 1992-10-20

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