JPS59154692A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To speed up data read speed by providing an MOS transister (TR) for discharging which discharges the charge on a data line coupled with plural memory cells so as to turn on an MOS TR7 when an address signal changes. CONSTITUTION:An MOS TR(Q)41 is connected between a circuit point S being an input terminal of a sense amplifier 36 and a reference potential point and an output signal from an NOR circuit 49 is inputted to its gate. Further, the output pulse from a pulse generating circuit 45 is inputted to the gate of a Q47 being a driving transistor to the NOR circuit 49 and the output signal from an inverter 44 is inputted to the gate of a Q48 being other driving TR respectively. Further, a signal at a connecting point between the Q46 and Q47, 48 in the NOR circuit 49 is inputted to the gate of the Q41 for discharge as an output signal in this circuit. A threshould voltage of said inverter 44 and a data sense level of the sense amplifier 36 are almost coincident with each other, then the discharge by the Q41 is attained in the vicinity of the sense level of the sense amplifier 36, thereby attaining the detection of data of the sense amplifier 36 in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Summary of the Invention The present invention relates to a semiconductor memory device using MOS transistors as memory cells, and particularly relates to an improvement aimed at increasing data read speed.

[Technical background of the invention and its problems]

If we consider a semiconductor memory device, for example, one in which a nonvolatile semiconductor memory element having a floating gate is used as a memory cell, this memory element has a structure as shown in FIG. Figure 1 (A) is a diagram of the pattern of this memory element, and Figure 1 (B) is its aa'
A cross-sectional view taken along the line, (C) is a cross-sectional view along the bb' line.
) is a diagram of ivy. (2) As shown in FIG. A floating gate 16 is formed in the second region 14 with an edge film I5 interposed therebetween, and a control gate 17 is further formed on the floating gate 16 with an insulating film 15 interposed therebetween.

In the memory element having such a configuration, data is programmed by increasing the threshold voltage Vth of the MOS transistor by injecting electrons into the floating gate I6. That is, in a state where the threshold voltage Vtb has increased, the control gate 1
Even if a trace level reading 1+ki pressure is applied to 7, it will not turn on. On the other hand, floating gate l6'
[I! When a child is not injected, when a continuous level reading pressure is applied to the control gate 17, the control gate 17 is turned on. And this A-fu autumn state or (
Data is read by making the 1-on state correspond to the logical "1" level or "0" level.

By the way, in the memory element as shown in FIG. In order to increase the current flowing through the element in order to increase the injection efficiency of the injector and to increase the readout speed during data readout, the potential of the floating ink gate 16, which is the effective gate, is set to about m of the control gate 17. It is necessary to raise it sufficiently when ascending. On the other hand, in this memory element, as shown in FIG.
As shown in the cross-sectional view of C), the control gate 17
A capacitance CI exists between the floating gate 16 and the floating gate 16, a capacitance C2 exists between the floating gate 16 in the field portion and the substrate 11, and a capacitance C2 exists between the floating gate 16 and the substrate 11 in the field portion, and a capacitance C2 exists between the floating gate 16 and the floating gate 16 on the channel region 14 and the channel region There exists a function ftCs between the 14 and 14 respectively. Now, when the potential VCG is applied to the control gate 27, the potential VFG of the floating gate l6 is given by the following equation.

As can be seen from this equation, in order to raise the "direction" of the floating gate 16, it is better to increase C1 compared to fil:Cs.One way to increase the capacitance C1 is to increase the floating gate 1g. There is a method of thinning the thickness of the insulating film 15 between the control gate 17. However, if this film thickness is made thinner, the electrons stored there will escape once they are injected into the floating gate 16. It becomes easier and there is a high degree of reliability 3.
Another method for increasing the above answer +1{c1 is to make the floating game 1/16 itself large. The distance νJ1t between the a-tink gate I6 and the base 11 constituting the valley C is equal to 7oooX, and the distance νJ1t between the a-tink gate I6 and the control gate 17 that constitute the valley C is The distance between is i(10
Since there is 0X degree of strength, C1 is larger than jin if you compare each - fist per unit of force. Therefore, while keeping the portion above the channel region I4 constant, the floating gate 16
Since C, is much larger than c2, the increase in size of c1 is larger than the increase in c2 + 03.

Figure 2 shows the memory elements shown in Figure 1. {
1 is a pattern plan view of a J combination in which the bond is distributed in a 71-lix shape in the 1 direction and the horizontal 1i direction to form a Hayabusa 7 bond. +J'l in the figure
In the I direction, there is a double express line 7iJ. ? 7, 2Z, . . . are formed to extend parallel to each other. These row lines 21
is a greenery corresponding to the control f'-t 17, and is made of a second layer of polycrystalline silicon, for example. A floating gate 16 made of a first layer of polycrystalline silicon is provided below the row line 2. Furthermore, n-diffusion layers 22 and drain layers which serve as source regions of each memory element are formed across each floating gate 16. n+ diffusion layer 2 which becomes the in region
3 is formed, and this n+ type diffusion layer Z2 is integrally formed for each row line.

In addition, the n4 type diffusion layer 23ζ is integrally formed for each pair of adjacent memory elements, and the wiring Hy24,z, which is the outer line of the ladle, is further formed to extend parallel to each other in the vertical direction.
Connected to 4,... Note that the memory element (MOS transistor) 25. , 25, . . . are formed at the intersections of each row line 21 and the wiring 24 serving as each column line.

In such a configuration, the lateral length of each memory element 25 is equal to the hatched area of the coating gate 1.
The length of 6 and the channel width W (are determined by this. On the other hand, in order to screen the degree of integration,
6 and the channel width W are required to be as small as possible. Therefore, in general, the channel Iffiw is set to the minimum value necessary to perform the transistor function.
At present, the size of the floating gate is determined so that the I level of the floating gate 11 is about 3V when the potential of . C, the mutual fundance of the memory element, 71I] is not very large, and V
1ooi for IFte where CG is 5V and drain voltage is 3■
tp. I can't seem to get enough output.

Figure i'i'g3 is a complete diagram of a conventional T{OM circuit 1 constructed using integrated memory elements as shown in FIG. The memory cells 31, 31, .
This corresponds to the memory element in the figure. Among these, the control gates C1 of the plurality of memory cells 31 arranged in the horizontal valley rows and the decoded outputs of the row Tecoder 32 are commonly connected to the corresponding one of the row lines 3.91 to 33n of the number of frames. Ru. Further, the drains of each of the plurality of memory cells 3l arranged in each column in the vertical direction are connected to algebraic data lines (wires serving as the column lines) 341 to 34. 1l are connected to corresponding ones of n.

The sources of the first number of memory cells 31 are connected in parallel to a reference potential point (earth potential). Furthermore, the plurality of data lines 34, - 34m are connected to the sense amplifier 36 via each of the plurality of column selection MOS transistors 351 - 35m.
is connected to the input end of the circuit, that is, to the circuit point S. The gates of the plurality of column selection 10S transistors 351 to 351n are connected to respective column line selection lines 381 to 38F+"l to which the decoded output of the column decoder 37 is applied. The gate and source of a tabulation type MOS transistor 39 as a load MOS transistor are commonly connected to the circuit point S at the input end of the transistor 36, and its drain is connected to the power supply voltage VDD application point. The unspecified MOS+1 range are all enhancement type.

In the ROM shown in FIG. 3, it is assumed that each memory cell 31 is programmed with data in advance. Now consider the case of reading data from a memory cell located at the intersection of one row line 331 and one data line 34l. S, in this memory cell 3I, the threshold value '
It is assumed that the heart pressure has increased and is set to about 6■. When the address signal changes so as to select this memory cell 31, the V column decoder 37 sets the column line selector 381's ``zei~}'' to the ``1'' level, and the connection is made to this. Column selection MOS transistor 3
5 vines are turned on.

Then, through this MOS} transistor 351, the MOS
The data line 34 is connected to the 1" level by the transistor 39. At the same time, the row taper 3 is connected to the 11N level.
2, the corner of the row line 33 is crossed to the "1" level. As a result, the memory cell 31 existing at the intersection of the row line 331 and the data line 34l is selected. However, this memory cell 3 The threshold voltage of is 6V% as mentioned above.
i'f, and the 11111 level output peak of the row decoder 32 when reading data is 5V, so this selected memory cell 31 is turned on, and the sense amplifier 36 outputs the data at this time, for example. Detected as 1n level.

Next, in this state, another memory cell connected to the same data line 341, for example Ii row line 33? Consider the case where data is extracted from the memory cell located at the intersection of the data line 341 and the data line 341. In this memory cell 3
Suppose that, unlike in the first case, the threshold value has not increased and remains low, for example, about 06■. This memory cell 3 is turned on and selected. By the way, since the data line 341 was previously charged to the "1" level by the MOS+- transistor 39, it is necessary to discharge the data line 34 through the memory cell 31' which is turned on. As a result, data is read out to the data line 341. However, like the previous 8L model, the current and driving ability of each memory cell 3 is... OO
It is consistently low, around μA. Therefore, it takes a long time for the sense amplifier 36 to detect the "0" level signal. In this way, the data readout time in a conventional ROM is limited by the discharge time of the data line 34 in the memory cell 31, and approximately half of the data Φ゛L readout time is spent on this discharge time. This has the disadvantage that the read speed is slow.

[Purpose of the starting moon]

This invention was made in consideration of the above circumstances, and its purpose is to provide a semiconductor memory device that can increase data read speed and brightness without increasing the size of each memory cell. It is about providing.

[Summary of the Invention 1-''P7.] In order to achieve the above object, the present invention provides a method for discharging a data line to which a plurality of memory cells are connected.
An OS transistor is provided, and the MOSI transistor is turned on when the address signal changes.

[Embodiments of the invention]

An embodiment of this invention will be described below with reference to the illustrations.
FIG. 4 is a circuit configuration diagram when the present invention is implemented in a ROM. In FIG. 4, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and their explanation will be omitted. Therefore, only the parts that are different from those in FIG. 3 will be extracted and explained. That is, the difference between this embodiment circuit and the circuit shown in FIG. An inverter 44 consisting of an enhancement-type MOS transistor 42 and an enhancement-type MOS transistor 43 generates a pulse signal with the required pulse width by detecting changes in the address signal.
An output pulse signal from the pulse generating circuit 45 and the output of the inverter 4 are input in parallel, and the output information is used to generate a MOS for fBe emission 1H.
Depletion type MOS transistors 46 and 211. which control on/off the I-transistor 4; ! i
2['Hancement No i4's Most・:7/J's7'747.4g to 4f7, made/'T(N
OR) circuit f-2 is provided 7・(!:koi・l
There it is.

-L? +i MOSI' run disk 41 (, 1' 6 (''.) is inserted between the circuit point S, which is the human power 01" 111 of the sense amplifier 36, and the R! potential point, and the 6" Nor circuit L-? is inserted into the gate. The output signal from - the bow is input. - The inverter mo/ is the one that inverts the information at the circuit point S.
Gate 1 of MOS transistor 47, which is an S transistor
-(Here, the output pulse from the pulse generation circuit 45 is
MOS for the other 1 rumor axis + 1 transistor.
} Gate 1 of transistor 48 t, 11 i/har
Output from Ta 4-no {No. ii- is that, ・2 is manually powered 3, ・Koshide/end circuit. 1 of the MOS transistor 46 and the MOS transistors 47 and 48 in i-2
``I#M'' is input to the gate of the MOS transistor 41 for abstinence as outputs 1 and -1 in this circuit. It should be noted that all of the MOS transistors added for which the type is not specified are of the enhancement type.

In such a configuration, the k66 connected to the same data line 34
2, which stores different data in advance.
The operation when reading data continuously from the memory cells 3I will be explained using the timing chart of FIG. One line now, l\}! 33+ and one data line 34
Consider the case where data is read from memory cell 3 located at the intersection with 1. Note that this memory cell 31
11 [詑, same as i. : D data program L temple ζ is the threshold 11. }"4?+.l,'vth or 6V in degrees. When this memory cell 31 is selected 7 times, the same i1:I'li (one data thread) !: 434, is raised toward the "1" level, and the heart I\11 of the row 331 is set to the "1" level. At this time, the threshold 1 of the selected memory cell 31 is set to the "1" level. The direct pressure is in the k8 state ζ, and this memory cell 31 is not turned on, so the data 341 remains charged to the "1" level.
b) The 4th position of the circuit point S, which is set to the same level as the data 1a4, is detected via the 4 selection MOS transistor 35, and the previous data is detected as, for example, the IIiu level.

Next, in this state; f, i, ij, now a:tt-x is adjacent to the same take freeze 134,)'Ij sa-I'C, and another memory cell is l;i:'iff]. Same as Iit12 +-C
At the intersection of the row line 332 and theta line 341, there is
Consider the case where data is read from the memory cell 31. In addition, in this memory cell 3, the threshold voltage 'i[' is not increased and remains in its original low state of about 0.6 V at the time of data programming, as in the previous i1[]. Before this memory cell 3I is selected, the potential at the circuit point S is at the "1n level. At this time,
The output IS' of the inverter 1 is at the ``1'' level, and the MOS transistor 48 in the Noah circuit 1k-!j is
On the other hand, in order to select the -12 memory cell 31, the state kI1 of the address 1g changes.Synchronizing with this, the pulse generating circuit 46 has the required pulse width. Outputs the ``0'' level pulse signal No. 1. Then, the MOSh transistor 47 in the NOR circuit Ly is turned off during the pulse width period of this pulse {fi. At this time, a pulse signal of {1''1'' level was output from the 4 NOR circuits, and the MOS of J11}
(S on.

On the other hand, when the address signal disappears, the potential of the row line 33 is set to the "1n level" by the row decoder 32, and the column selection MOS+- transistor 35 is set by the output number of the decoder 37. ] and data line 3.
4, is coupled to circuit point S. Since the threshold voltage of the memory cell 31 selected at this time is low, it is turned on thereafter, and the data +N34+ and the circuit point S are discharged together. By the way, as mentioned in Section 2 I7, after the address information changes, the MOS transistor 4 connected to the circuit point S and having a sufficiently large driving capacity
1 is turned on, this MOS} transistor 41 is mainly used to input -1 data. J) 1341-. Correction circuit point S is released.

Therefore, the memory cell. ? The dimensions of 7 are small for the size of the sieve.
・，?・1) Even if the l power is low, is it possible to release the data 5134t and the circuit point S to a certain level? ，! ” Since rj7 is plotted among the samurai, sense-1'nzo3G4 + t,'+711ii;j of "0" level take in Choichi;
te-'F: Can be performed faster than te-'F:. That is, the read speed 7B of data when θ8 is greater than that of slave-1. 'l. A+j becomes 1X.

Na-T, I, Juki-To 1.14 R5 in total 11 circuits,
I7. j1]
-C
(The old address 1 Shougetsu's -5'J [circle that captures the single and rising F changes; []'s 1-ranjishi 1 day technique circuit, etc. is used as a toy.

Ding V, - to old 11 actual L"n.i1 冫1川I? F, 'C
, t+ is the inverter (-!'s output 11 goes to the 01'' level and the MOS transistor 48 is turned on), and furthermore, the MOS transistor 4I for release r't becomes A and this MOSI transistor 4 is turned on. Therefore, the circuit threshold of
'tf (If the voltage and the data sense level of the sense amplifier 36 are made to substantially match, the control by the 08 transistor 41 to Δ is carried out up to the vicinity of the sense level of the sense amplifier 36, and as a result, the data is detected in the sense amplifier 36.・It can be done in a short period of time.

This invention is described in the above embodiments. In what is completely repeated, the transformation of 7I<Gods is pJ Noh. For example, -” 2 Acts
1. MOS for absentmindedness in gi! -Langister 4/6
-Circuit point S at the input end of sense 1' block 36 ('?')
(-J1 When this circuit point S is at the "1" level, this R'lOS} turns on the transistor 4J and discharges to 1-f.
I explained the case where this happens, but this (, ↑, each data storage (341 to 34,.)
A transistor may be provided to turn on these MOS transistors for a predetermined period of time. The cell 3l is a non-volatile semiconductor memory element which has a floating gate as shown in FIG.
It may also be a memory element of i'T configuration.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a semiconductor eight-chip memory device that can increase the speed of data readout without significantly changing the dimensions of each memory cell.

[Brief explanation of drawings]

Figures 1 and 1 are diagrams showing the configuration of a non-volatile memory element,
2nd ['21i; 4 and 4 south are circuit diagrams of an embodiment of the present invention, and FIG. 5 is a timing chart of the circuit shown in FIG. 3. Memory cell, 32. Row decoder, 33.
...Row line, 34...Data line, 35...M for column selection
OS transistor, 36... sense amplifier, 37...
- Column decoder, 3B... Column line selection line, 39... MOS transistor for load, 41... MOS transistor for discharge, 44... Inverter, 45... 71° pulse generation circuit, 49 ...Noah circuit. 483 484

Claims (3)

[Claims] (1) At least one data line to which an initial number of memory cells are coupled, a charging means for charging this data line to a predetermined potential, and a charging means for charging the data line to a predetermined potential when the address signal changes. ↑ ``A semiconductor memory device characterized by comprising means. (2) - The semiconducting body storage device according to claim 1, wherein the discharging means is configured to perform discharge only when the 1' position of the theta line is equal to or higher than a predetermined level. (3) The discharging means sets d1 in the first term of the sensing range to be formed by I'i(,j) so that the discharge occurs near t when the sense level of the sense amplifier connected to the data line is I=t. l
and semiconductor storage devices.