JPS5812193A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the power consumption, by suppressing the instant peak current when a memory access is under working with a precharging circuit that charges a pair of bit lines which serve to transfer a data to a memory cell. CONSTITUTION:The MOS transistors TR T6 and T7 which receive the supply of the 2nd precharge signal PC2 at each gate are connected between a power supply Vcc and a pair of bit lines Qn and Qn'. Furthermore an MOS TR T8 is connected between the lines Qn and Qn'. In this case, the signal PC2 is set at zero level when the Vcc is higher than a prescribed potential and then set at the same level as the 1st precharge signal PC1 when the Vcc is lower than a prescribed potential respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory, and particularly to a semiconductor memory that randomly reads and
This relates to writable random access memory (RAM).

In recent years, there has been a gradual increase in the number of systems in which the internals are operated in one step. This is for the purpose of reducing current consumption or improving operating speed by performing one dynamic operation.

Even if they do not have a very dynamic operation, many integrated circuits generate clock pulse signals within the integrated circuit for initializing or precharging the internal nodes of the integrated circuit g1m, and this is also done for the above-mentioned purpose.

As mentioned above, the lock pulse signal or the signal for dynamic operation is generated in synchronization with the chip enable signal (signal for placing the chip in the operating state IHc) input to the integrated circuit, or when the address signal of the memory changes. It is created in sync with the. Due to the clock pulse signal generated in this manner, the current associated with charging and discharging for initializing olI flows as an instantaneous peak current during operation.

Generally, these charging and discharging currents increase dramatically because the stray capacitance associated with the li1 main signal increases, which increases the memory capacity. Also - the faster the operating speed of the device, the more charging and discharging of these stray capacitances must be encountered (thus, the charging and discharging currents also increase sharply, causing the input signal or memory chip to This not only adversely affects the operating margin of the circuit, but also increases the level of difficulty in mounting technology.

For example, in a memory system that detects a change in an address signal and generates a clock pulse signal for controlling the inner sg circuit in synchronization with the change, charging and discharging of the inner sg circuit using this clock signal is required. This caused a noise in the electric wire as if it had been tampered with, and this noise threatened to generate a clock pulse signal again, creating a false possibility that the circuit would oscillate.

As mentioned above, the instantaneous peak current becomes larger when a large stray capacitance is charged and discharged in a short period of time. In a semiconductor memory, places where this large amount of stray capacitance exists are the memory cell, bit 1, and the like. Conventionally, this bit line was precharged at the same time on all pages, so the instantaneous peak current for precharging this bit line was much larger than that for charging and discharging other internal boards.

A typical example of such a semiconductor memory that performs dynamic operation is shown in Fig. 1111. On the right side of this diagram, the memory cell l driven by the selected row 118L stores its memory. Information on a pair of pins) II
It is designed to output to Qrs and Qn. Then, the pair of data output to Qa and Qa have opposite phases to each other, and this data is
The sensor amplifier I detects and outputs the signal. Furthermore, usually the line @I! For keys in which L is selected, the precharge circuit 5 precharges IIQm-9 to a predetermined potential level.

Conventional III% of the precharge gllllJ - shown in Figure 2, MOB) Ushisister T,,'I'
.

Arranges between electric mVcg and bit IIQfi! The gate of the transistor 〒1 is connected to the voltage 11Vccjζ, and the precharge signal PC is input to the gate of the transistor 〒1.Also, the MOB) transistors T, , T are connected to the power supply Vcc and the bit 1lQl. The gates of the seven transistors are connected in parallel between the
``hcic* is connected, and the above signal PC is input to the gauge of the transistor T.Furthermore, two pins) II
A MOB transistor transistor whose gate receives the signal PC is connected between Qn and Qa. Transistor here! i, terrorism acts as a load transistor for memory cell l, transistor! ■、! , is the signal P
Electricity 1 due to C! IVccη) Rahi) l[Qm −Q
The transistor T operates as a storage transistor for charging the bit ilQ.
It works to equalize the potential of a.

In the predetermined mode as described above, precharging of Qn is started. In other words, when the precharge signal becomes pcffi@1'' level, the transistors ?, , T are conductive, and the bit 1IQa becomes conductive.

Qn is charged. At this time, bit II (am) is charged until it reaches the same potential as bit 11QII, and this charging current appears as a peak current. Therefore, when charging the bit line capacitance, which becomes relatively large as the capacitance increases, A large instantaneous peak current flows, which creates a lot of noise and affects the operation of the circuit.

The present invention has been made in consideration of the above-mentioned circumstances, and data reception for one memory cell is performed using a pair of bits l! Therefore, when the power supply voltage is above a predetermined voltage, the pair of bits II are short-circuited, and when the power supply voltage is below a predetermined voltage, the pair of bits S! T- short circuit and power St # 9? It is an object of the present invention to provide a semiconductor memory 9 that can reduce current consumption by suppressing instantaneous peak current during a memory access operation, increasing the all operation margin and increasing the single operation speed W by increasing the memory access operation.

Hereinafter, an embodiment of the present invention will be explained with reference to 1lII.

Figure 134 shows a precharge circuit for a cow conductor memo as described above with reference to 1ml.

The first path is the power supply VC+C and a pair of pins) IiQzena Qt
M08 transistors T1 . Te! are connected to each other, and a transistor MJ8) whose gate receives the III precharge signal Pct is connected between the bits Qn and Q. In this case, when the voltage 1111Vcc is higher than the predetermined potential, the I8282 bridge signal Cj is -O level, and the voltage @Vc
When c is below a predetermined potential, the 82 bridge signal Pct becomes the same signal as the 1111 push signal PCJ. In addition.

The precharge signal PCJ of III is a signal similar to the precharge signal PC of FIG. 112 described above.

The operation of the first precharge path having the above configuration will be explained with reference to the signal waveform diagram of jlIslll. In the 5th III,
A solid line indicates when the power supply Vcc is above a predetermined voltage, and a broken line indicates when the power supply VCC is below a predetermined voltage.
The key for selecting 8L is that the first signal PCJ goes to the "l# level. At this time, if there is a transistor, the charge on the bit QalZ) moves to the pin)l[Qn, so that both Beep) III Qm, Qn
are at the same potential. At this time, bit II Qm has the same potential. When C, beep) When charging IIQII, beep)
The charge of II Qfi has no relation to the source vcC, so a large instantaneous peak current does not flow when charging the bit.

However, simply shorting Qm and Ql as described above will cause a problem when the potential of the power supply Vcc drops. That is, at this time, 1, for example, the @1 level of bit line Qm decreases in accordance with the voltage 11Vcc potential, causing a beep) II
The potential after the short circuit of Q-Q #Q-Feng may be too low and be out of the sensitivity of SEISUAB1, or it may be beep)II! Since the potential of Ql"e- is too low, when reading data from one cell 1xih, the data in memory cell 1 is reversed, that is, @
There is a possibility that a write-in may occur from "O" to "L".In other words, if only the first charge signal PCI is used, a problem arises in that the power supply margin becomes small.

On the other hand, when the voltage m"lc@ becomes lower than the predetermined potential, the $2 precharge signal rCI also becomes the @18 level at the same time as the first precharge signal PCJ. The voltage waveform at this time is
In other words, the operation at this time is almost the same as the case shown in Figure 3 when the value has been reached, but the charging potential difference becomes smaller by the amount that the electromagnetic gc is lowered, and the instantaneous peak current decreases accordingly. will also decrease. The charging/discharging current I in this case is calculated by Tsugitake.

Δ1 Here, C is the capacity to be charged, ΔV is the potential difference to be charged, and the time required for charging 31 years.

In other words, from the above equation α), if the potential difference ΔV is small, the charging voltage RI will also be small (ゎη), that is, the voltage 111
When 1Vc-cffi is high, bits JIQm and Qn are smoked by transistor T, and the charge accumulated in one bit line charges the other bit line, reducing the instantaneous peak current flowing from the current to approximately zero. For Noku, power supply VC
When @ becomes low, transistor T- is made conductive, and simultaneous transistor T-0T is also made conductive. Furthermore, since the power supply VCC is lowered, the voltage difference ΔV between the two and the charging voltage is also smaller, and the instantaneous peak current is correspondingly smaller.

Therefore, the semiconductor memory of the above embodiment has the advantage that the power supply margin is wide and the instantaneous peak current is small.

No. fNIJ indicates a precharge circuit according to an embodiment of the present invention. This Bridgeage Igl path is a modification of the fourth alIOJ circuit described above, with gates connected to the voltage Vcc and IIQII and Qfi, respectively.
cc#c connected load N08 transistor T-, T1
6 is connected, and the other parts are the same as the iJ4 diagram. Of course, transistors 'I',,T,. can be anything that can act as a load, for example, it can be a simple resistor. Even in this precharge circuit, the transistor %-
If the conduction resistance of Tss is sufficiently large, there is no effect on the instantaneous peak current, and the same effect as in the embodiment described in III is obtained.

On the right, in the above embodiment, the precharge signals PCr and Pct of %III and 112 were made to be @0" as the key for newly selecting row @8L, but the selection of row @8L and the precharge signal Pt1 It goes without saying that 11 rubles may overlap.

Seventh! I is a line for generating the first precharge signal PC1 used in the semiconductor memory of the present invention. ccIJ
The path a is a depletion type M08 transistor TIf + ' connected between the power supply VCC and the ground.
rul T1. and an enhancement type MO8) run sister a Ti4 a Tl are each configured with a two-stage inverter Ileum and a buffer circuit Blk, and the output nA of the first stage inverter is transferred to the second stage I/part! , the gate of transistor T14 and buffer circuit B
1 transistor T1. The output terminal of the second stage inverter is connected to the gate of the buffer circuit B.
Connect one end of the capacitor C to the output terminal of the transistor "11@'r" of this buffer circuit B, and connect the gate of the transistor 11 of the buffer circuit B to the output terminal of the transistor "11@'r," and connect the transistor 8 of the station 8 whose gate is connected to the power supply VccK. The lock pulse φpolcli for precharging is continued through the gate.This clock pulse φP0 is applied to the transistor To of the first stage iterter!
By adding it to the gate of the transistor T11
The first precharge signal Pct is obtained from the output terminal of the circuit.

In the above circuit, the precharge clock pulse φ
When P0 reaches '1 level, the other side of the capacitor C is charged to the transistor through 8, so that the potential level of the signal PCI line rises.

At this time, the first stage inverter ■1 transistor T'ts
is turned on, the transistor 7161''1- is turned off, and one side of the capacitor C is at the l'' level.

Moreover, at this time, since the signal PCt line has already been charged to a certain potential, the capacitive coupling of the capacitor C raises this signal PCJ to a potential higher than the voltage m_vcc. Therefore, charging and discharging of pins IIQn and - will be carried out quickly.
This is one path that generates 12 precharge signals pcz.

This path a is connected in series between the electric @ Vcc and the ground, respectively.
Tel m-2- and 4-stage inverter I, respectively.
~■6 and buffer circuit B constitute a five-stage circuit.

Furthermore, the gate of the first stage inverter I is connected to the power supply VCC.
resistance tcWsmR of the voltage divider circuit provided between
connected to interconnection point 1 of m, 311! The output terminal of the second inverter Ia receives the inversion precharge clock pulse φp.
It is configured to be connected to the gate of the transistor TsI of the final stage buffer circuit B1 while being grounded via the M08 transistor T to which the signal C is applied. And the first stage inverter! Turtle's Try) Star T'to
A predetermined voltage signal from the voltage divider circuit is input to the gate of the transistor, and an inverted clock pulse φ is input to the gate of the transistor.
pct-The second precharge signal PCJ is manually obtained from the output stage of the final stage buffer circuit B1.

In the above circuit, the II2 precharge signal PCJ is generated when the power supply VCC becomes lower than a predetermined potential. That is, now the resistor Rsk40 is 8, and the resistor R is 1
If Ω is set to 0, the potential at the connection point a is 0.2 vcc
becomes. Therefore, the inverter I, cD question value voltage is 0.8
If power is connected to v, if the power supply vcc is 4v or more, the star point potential will be 0.8v or more, and if the electric power fiVcc is 4v or less, the 1-point area will be 0.8v or less. Therefore, the output of the inverter 11 is at the 0" level if the voltage 5vtc is 4V or more, and is at the "1" level if it is 4V or less.

Therefore, if the electric mV@@ is more than 4V, use an inverter! , the output of the inverter 1 becomes the @fil level, the output of the inverter 1 becomes the '08 level, and the output of the inverter ■- becomes the °02 level regardless of the clock pulse φpc, so the second precharge signal PCj becomes the @Om level. Become. Conversely, if the power supply Vcc becomes 4V or less, the output of the inverter 11 will be
1” level.

The output of inverter ■ becomes °0 level, and the output of inverter
In synchronization with the change in m, the level becomes 11'', and in synchronization with this, the level l$2 precharge signal PCj increases to 1m1m level l$2.
The transistors T--Tma of the precharge circuit shown in FIGS. II41m and W6 described above are driven by this. In addition,
Inverter in Figure 8! It goes without saying that the circuit shown in Fig. gJ7 may be used instead of the 6-puffer circuit B1.

In the semiconductor memory of the present invention, the above-mentioned tJ7 diagram and 11
In the signal generation circuit shown in FIG.
, PCJ drives the precharge circuit shown in FIG. 114 or FIG.

As explained above, according to the present invention, data is received and transferred to a memory cell using a pair of pins) II
When the power supply voltage exceeds a predetermined voltage, the pair of bits I! When the power supply voltage is lower than a predetermined voltage, the pair of pins (IN) are short-circuited and precharged by the power supply, so that the instantaneous peak current during memory access operation is suppressed and the power consumption R is reduced. A semiconductor memory that can increase the circuit operation margin and improve the operation speed can be provided.

[Brief explanation of drawings]

Figure 111 shows an example of the thin y-II configuration diagram, and Figure 2 shows 1
113 is a waveform diagram for explaining the operation of the circuit shown in 1112, and 114
The figure is a line diagram showing the precharge circuit of the cow conductor memory device according to the 1* and m examples of the present invention, and the wS diagram is 1141! The sixth factor is a circuit W showing a precharge circuit of a semiconductor memory according to another embodiment of the present invention.
A% 11711 and FIG. 8 are circuit diagrams showing signal generation circuits for driving the circuits of FIG. 1184 and FIG. 6, respectively. 1-・Method cell, 2-・Sense amplifier, 1・-Pdecharge circuit, 8L-row line% Qfi a Qn...Beep) 11[%PCJ, PC! - Precharge signal, T section ~ 1mer transistor % VCC - Power supply Takehiko E Takehiko, patent attorney, patent attorney Figure 2 Qn Qn Figure 3 Qn Figure 4

Claims (1)

[Scope of Claims] 0) A plurality of memory cells for storing data, a row line for selecting and driving a memory at a predetermined location from these memory cells, and a pair of data cells for storing data from the memory cells. If the voltage of the pair of bits received and 411111 exceeds a predetermined value, the pair of pins) IIt-4m1 will be connected, but if the voltage of the power supply is less than a predetermined value, the pair of pins will short-circuit and the pair of pins will short-circuit. A semiconductor memory is provided with a precharge circuit that charges the memory by a power supply, and suppresses instantaneous peak current during memory access operation. (2) The puttage gIIIM is connected between the pair of bit lines and is operated by the 111 bit line signal to bring the pair of bits to the same potential. A pair of pins are connected between the lines and operated by the 19Jz precharge signal.
2.118th transistor to push I and l
Patent claim 11111 is characterized in that it has the following features:
The semiconductor method according to item 11. (2) The preacher current path is a first transistor connected between the pair of bits 1 and operated by the III preacher e signal to bring the pair of bits II to the same potential;
# A gun is inserted between the electric keyaki and a pair of bit lines 8
The WZ and *S transistors, which operate with two output signals to put a pair of bit acids, are connected in parallel with the above-mentioned WS transistors between the power supply and the pair of bit lines. 52. The conductor method according to claim 51, characterized in that it comprises a fourth load transistor and an s-th load transistor. α) The semiconductor memory according to claim @@Ig2 or jI8, wherein the second precharge circuit is generated when a memory cell is selected by the row line.