JP3133706B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device capable of storing analog information and multi-valued information by a memory cell transistor having a floating gate.

[0002]

2. Description of the Related Art An electrically erasable programmable ROM (EEPROM: Elmer) in which a memory cell comprises a single transistor.
(ectrically Erasable Programmable ROM)
Each memory cell is formed by a transistor having a double gate structure having a floating gate and a control gate. In such a memory cell transistor having a double gate structure, data is written by accelerating and injecting hot electrons generated on the drain region side of the floating gate into the floating gate. Then, data is read by detecting a difference in operation characteristics of the memory cell transistor depending on whether or not charge is injected into the floating gate.

FIG. 5 is a plan view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate.
FIG. 6 is a sectional view taken along line XX. This figure shows a split gate structure in which a part of the control gate is arranged side by side with the floating gate. A plurality of isolation regions 2 made of a selectively thick oxide film (LOCOS) are formed in a strip shape in a surface region of a P-type silicon substrate 1 to partition an element region. A floating gate 4 is arranged on a silicon substrate 1 with an oxide film 3 interposed between adjacent isolation regions 2.
This floating gate 4 is arranged independently for each memory cell. Also, the oxide film 5 on the floating gate 4 is formed thick at the center of the floating gate 4 and makes the end of the floating gate 4 an acute angle. This makes it easier for electric field concentration to occur at the end of the floating gate 4 during the data erasing operation. On the silicon substrate 1 on which a plurality of floating gates 4 are arranged, control gates 6 are arranged corresponding to each column of the floating gates 4. The control gate 6 is arranged so that a part thereof overlaps the floating gate 4 and the remaining part is in contact with the silicon substrate 1 via the oxide film 3. The floating gate 4 and the control gate 6 are arranged such that adjacent rows are plane-symmetric with each other. N-type first diffusion layers 7 and second diffusion layers 8 are formed in a substrate region between control gates 6 and a substrate region between floating gates 4. The first diffusion layers 7 are surrounded by the isolation regions 2 between the control gates 6 and are independent of each other.
The second diffusion layer 8 continues in the direction in which the control gate 6 extends. These floating gate 4, control gate 6, first diffusion layer 7, and second diffusion layer 8 constitute a memory cell transistor. Then, aluminum wiring 10 is arranged on control gate 6 via oxide film 9 in a direction crossing control gate 6. This aluminum wiring 10 is connected to first diffusion layer 7 through contact hole 11.

In the case of such a memory cell transistor having a double gate structure, the on-resistance between the source and the drain varies according to the amount of charge injected into the floating gate 4. Therefore, by selectively injecting an amount of charge corresponding to the stored information into the floating gate 4, the on-resistance value of a specific memory cell transistor is changed in an analog manner, and the operating characteristic of each memory cell transistor caused by this is changed. The difference is associated with the data to be stored.

FIG. 7 is a circuit diagram of the memory cell portion shown in FIG. In this figure, memory cells are divided into 4 rows × 4
This shows a case in which they are arranged in columns. In the memory cell transistor 20 having the double gate structure, the control gate 6 is connected to the word line 21 and the first diffusion layer 7 and the second diffusion layer 8
Are connected to the bit line 22 and the source line 23, respectively. Each bit line 22 is connected to a select transistor 24
Is connected to the data line 25 via the. A sense amplifier (not shown) for reading a voltage value is connected to each bit line 22. Then, a write clock φW having a constant period is applied to each memory cell transistor 20 from the source line 23, and a read clock φR is applied from the data line 25. In a normal device, the control gate 6 itself commonly formed by the memory cell transistors 20 in the same row is used as the word line 21 and the aluminum wiring 10 connected to the first diffusion layer 7 is used.
Are used as the bit lines 22. The second diffusion layer 8 extending in parallel with the control gate 6 is connected to the source line 2.
Used as 3.

[0006] The row selection information LS1 to LS4 are generated based on row address information.
By selecting one of these, a specific row of the memory cell transistors 20 is activated. Column selection signals CS1 to CS
Numeral 4 is generated based on the column address information, and activates a specific column of the memory cell transistors 20 by turning on one of the selection transistors 24. Thereby, one of the plurality of memory cell transistors 20 arranged in a matrix is designated according to the row address information and the column address information, and is connected to the data line 25.

When writing data to the memory cell transistor 20, a ground potential (eg, 0V) is applied to the memory cell transistor 20 from the bit line 22, and a write potential (eg, 14V) is applied to the memory cell transistor 20 from the source line 23. I do. Thus, data is written in the specific memory cell transistor 20 selected in response to the row selection information LS1 to LS4 and the column selection information CS1 to CS4, that is, charge is injected into the floating gate 4. When reading data written in the memory cell transistor 20, the read potential (for example, 5) is applied to the memory cell transistor 20 from the bit line 22.
V) from the source line 23 to the ground potential (for example, 0
V). At this time, a current flows through the selected memory cell transistor 20, and the potential of the bit line 22 changes according to the on-resistance value of the memory cell transistor 20, so that the bit line potential is read by a sense amplifier. You.

When writing analog information to the memory cell transistor 20, the charge injection (write) and the check of the injection amount (read) are repeated in a short cycle in order to improve the recording accuracy. That is, reading is performed each time while writing to the memory cell transistor 20 is performed little by little, and the writing is stopped when the read result matches the content of the data to be stored. That is, as shown in FIG. 8, the write clock φw and the read clock φR are set to phases opposite to each other, and a write potential or a read potential and a ground potential are respectively applied to the bit line 22 and the source line 23 at a constant cycle. Are applied alternately. As a result, the period during which the write clock φW is raised, the write potential is applied to the source line 23, and the ground potential is applied to the bit line 22 is (W) the write period. Further, a period (R) in which the read clock φR rises to apply the read potential to the bit line 22 and apply the ground potential to the source line 23 is the write period. Then, in the read operation, the write clock φW is configured to stop when the read result reaches a desired potential associated with the stored information, and the write operation ends.

[0009]

The write clock φW
Is set to be higher than the read clock φR (about three times in FIG. 8) in order to ensure that the memory cell transistor 20 can inject charges into the floating gate. Generally, when the operating power supply of the device is 5V,
The read clock φR is generated by directly extracting the power supply potential, while the write clock φW is generated by boosting the power supply potential by a booster circuit. For this reason,
The circuit for generating the write clock φW has a complicated circuit configuration, and it is not easy to control the start / stop of clock supply.

An object of the present invention is to simplify the configuration of a control circuit for writing and reading.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has a first feature that an electrically independent floating gate is provided,
A memory cell transistor that changes the on-resistance value according to the amount of charge stored in the floating gate;
A source line connected to the source side of the memory cell transistor, a bit line connected to the drain side of the memory cell transistor, and a signal connected to the bit line, which associates the potential of the bit line with storage information. A first potential is repeatedly applied at a fixed period from the source line to the comparison circuit for comparing the potential with the memory cell transistor, and a second potential is applied simultaneously with the application of the first potential from the bit line. Alternatively, a third potential having a smaller potential difference with respect to the first potential than the second potential is applied, and the bit line is supplied via the memory cell transistor via the memory cell transistor during a gap between application periods of the first potential. And a write / read control circuit for flowing a current to the source line. The write / read control circuit selects the memory cell transistor. After being initially set in synchronization with the operation,
A latch for latching an output of the comparison circuit, and a first switch for transmitting an output of the latch to the bit line in response to a clock having a fixed period synchronized with a timing at which the first potential is applied to the source line And a second switch transistor for connecting the bit line to a current supply in response to an inverted clock of the clock, wherein the second potential is changed until the potential of the bit line reaches the signal potential. And the third potential is applied after reaching the determination potential.

According to the present invention, the second potential applied from the bit line to the drain side is switched to the third potential while the first potential applied to the source side of the memory cell from the source line remains unchanged. Thus, writing to the memory cell transistor can be stopped. The first potential which is higher than the second potential may be continuously applied to the source line at a constant period, so that the configuration of a circuit which supplies the first potential to the source line is simplified.

A second feature is that a plurality of memory cell transistors arranged in a matrix having an electrically independent floating gate and changing an on-resistance value according to the amount of charge stored in the floating gate. A source line commonly connected to a source side of the plurality of memory cell transistors; and a plurality of source lines arranged corresponding to each column of the memory cell transistors and connected to a drain side of a memory cell transistor in the same column. A plurality of bit lines, a plurality of comparison circuits respectively connected to the plurality of bit lines and individually comparing each potential of the plurality of bit lines with a plurality of determination potentials associated with storage information; and the plurality of memory cells. A first potential is repeatedly applied to the transistor from the source line at a constant cycle, and the first potential is applied from the plurality of bit lines. At the same time as the application of the first potential, the second potential or a third potential having a potential difference smaller than the second potential with respect to the first potential is applied. And a plurality of write / read control circuits for flowing a current from the plurality of bit lines to the source line via the plurality of memory cell transistors, wherein the plurality of write / read control circuits perform a selection operation of the memory cell transistors. And a latch for latching the output of the comparison circuit after being initialized in synchronization with the output of the latch in response to a clock having a fixed period synchronized with the timing at which the first potential is applied to the source line. And a second switch for connecting the bit line to a current supply in response to an inverted clock of the clock. Includes a switch transistor, the potential of the plurality of bit lines and applying the second potential to reach the signal voltage, after reaching the determination potential is to apply the third potential.

According to the present invention, the second potential individually applied to each column from a plurality of bit lines is independently controlled while the first potential applied to each column from the source line is kept unchanged. Then, the writing to the memory cell transistor can be stopped by switching to the third potential. Since it is only necessary to continuously apply the high potential of the first potential to the source line at a constant period for the memory cell transistors in a plurality of columns, the configuration of a circuit for supplying the first potential to the source line is simplified.

[0015]

FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention.
Is a timing chart for explaining the operation. The memory cell transistor 30 has the same structure as the memory cell transistor 20 shown in FIG. 5, has a floating gate and a control gate, and changes the on-resistance value according to the amount of charge injected (stored) in the floating gate. . The word line 31 is connected to the control gate of the memory cell transistor 30, and receives a row selection signal LS that is activated in response to the row selection information. The bit line 32 is arranged in a direction crossing the word line 31, is connected to the drain side of the memory cell transistor 30, and is connected to a comparison circuit 34 described later. The source line 33 is arranged in parallel with the word line 31 so that the memory cell transistor 3
0, and a write clock φW having a constant period is applied. As a result, the memory cell transistor 30 is connected in parallel to the bit line 32 and receives a predetermined potential from the bit line 32 and the source line 33 for each operation of writing, reading, and erasing.

The comparison circuit 34 calculates the potential VBL of the bit line 32
Is compared with the input information potential VIN associated with the storage information, and a determination output C0 that is inverted when the bit line potential VBL exceeds the input information potential VIN is generated. The write / read control circuit 35 is connected to the bit line 32 and supplies a power supply potential or a ground potential to the bit line 32 in response to the read clock φR and the determination output C0 of the comparison circuit 34.

The write / read control circuit 35 comprises, for example, three transistors T1, T2, T3, two inverters C1, C2 and one NAND gate A1. The readout clock φR is applied to the gate of the third transistor T3, and the third transistor T3 is connected in series between the bit line 32 and the power supply. The transistor T3 enables current to be supplied to the bit line 32 in response to the read clock φR, and also functions as a load resistor for reading the state of the memory cell transistor 30 during the read operation. The first inverter C1 is formed of a CMOS circuit, and is configured by a combination with a NAND gate A1.
It constitutes a latch that can be initialized by the reset clock φP. That is, the output of the inverter C1 is applied to one input of the NAND gate A1, the reset clock φP is applied to the other input, and the output of the NAND gate A1 is applied to the input of the inverter C1. Thereby, after the reset clock φP is reset during the low level period and the output is initialized to the ground potential, the potential applied to the input of the inverter C1 is latched. The first transistor T1 has, on its gate, a read clock φR inverted by a second inverter C2.
Is applied between the bit line 32 and the latch (the output of the inverter C1). Then, the read clock φR is applied to the gate of the second transistor T2,
It is connected between the comparison circuit 34 and the latch (input of the inverter C1). Therefore, the read / write control circuit 3
Reference numeral 5 supplies the power supply potential during the period when the read clock φR rises, and supplies the ground potential when the judgment output C0 is at the high level and supplies the power supply potential when the determination output C0 is at the low level during the fall.

As shown in FIG. 2, the write clock φW and the read clock φR are the same as the write clock φW and the read clock φR in FIG. 8, and have phases opposite to each other. The period during which the write clock φW rises and the read clock φR falls is the write period (W), and the period during which the write clock φW falls and the read clock φR rises is the read period (R). Also, reset clock φP
Is a selection operation of the memory cell transistor 30, for example,
In synchronization with the row selection signal LS applied to the word line 31, the memory cell transistor 30 rises from a low level to a high level when the memory cell transistor 30 is activated, and falls from a high level to a low level after a predetermined write operation is completed.
In the timing chart of FIG. 2, an operation margin is not set for switching each operation, but in an actual operation, the write clock φW and the read clock φR are temporarily reduced to 0 V to turn off each transistor. Such a period is set. Also, in order to prevent the ON periods of the transistors T1 and T2 of the write / read control circuit 35 from overlapping, the rising of the read clock φR is delayed by the inverter C2. The inverter C2 is provided only on the gate side of the transistor T1 and is provided only on the gate side of the transistors T2 and T3 (in this case, the read clock φ
The phase of R is the same as that of the write clock φW. )

While the reset clock φP is at the low level, the output of the latch (inverter C1) is at the low level regardless of the output of the comparison circuit 34, and writing to the memory cell transistor 30 becomes possible. Even if the reset clock φP rises in such a state, the writing to the memory cell transistor 30 is continued until the output C0 of the comparison circuit 34 goes high.

The potential VBL of the bit line 32 becomes the potential supplied from the write / read control circuit 35 during the writing period, and the power supply potential is turned on by the memory cell transistor 30 and the transistor T3 serving as the reading load during the reading period. The potential is divided by the ratio with the resistance value. When the memory cell transistor 30 is in the erased state, the on-resistance value of the memory cell transistor 30 is the transistor T3
, The bit line potential VBL substantially coincides with the ground potential. At this time, if the input information potential VIN is intermediate between the ground potential and the power supply potential, the bit potential VBL becomes lower than the input information potential VIN, so that the judgment output C0 goes high. Therefore, the write / read control circuit 35 supplies the ground potential during the write period.

When the write operation is repeated and the on-resistance value of the memory cell transistor 30 increases, the bit line potential VBL in the read period gradually increases as shown in FIG. When the bit line potential VBL exceeds the input information potential VIN during a certain read period, the judgment output C0 of the comparison circuit 34 is inverted. Thus, in the next writing period, the power supply potential is supplied from the writing / reading control circuit 35 to the bit line 32. Therefore, the potential difference applied to the memory cell transistor 30 between the bit line 32 and the source line 33 becomes smaller by the power supply potential than before the fall of the judgment output C0, and the writing in the memory cell transistor 30 is performed. Operation is stopped.
Note that the write clock φW is continuously supplied without changing the peak value.

After such a write operation is completed, the memory cell transistor 30 is in a non-selected state, for example, the row selection signal LS is turned off to turn off the control gate, and further, the reset clock φP is turned down to perform writing. / Read control circuit 35 is initialized.
Thus, in the case where a plurality of memory cell transistors 30 are connected to one bit line 32 in parallel, it is possible to sequentially write data by switching addresses for each memory cell transistor 30. Become.

In the above-described device, the same operation as when the peak value of the write clock φW is lowered is performed in the memory cell transistor 30 without changing the peak value of the write clock φW itself. For this reason, the write clock φW itself that becomes a high voltage does not need to control the peak value, and can be generated using a circuit having a relatively simple configuration.

FIG. 3 is a circuit diagram showing a second embodiment of the nonvolatile semiconductor memory device of the present invention, and FIG. 4 is a timing chart for explaining the operation thereof. The memory cell transistor 40 shown in FIG.
Is the same as This memory cell transistor 40
Are arranged in a matrix of, for example, 4 rows × 3 columns. Word line 4
1 is arranged corresponding to each row of the memory cell transistors 40, and the control gate of each memory cell transistor 40 is connected. Row selection signals LS1 to LS4 supplied from a row decoder (not shown) that receives row selection information are applied to the word line 41, and any one of the rows is selectively activated. Bit line 42 extends in the column direction in which memory cell transistors 40 are arranged,
The drain side of each memory cell transistor 40 is connected. The source line 43 is arranged to extend in a direction intersecting the bit line 42, and the source side of each memory cell transistor 40 is connected. Thereby, each memory cell transistor 40 is connected in parallel to the bit line 42 and receives a predetermined potential from the bit line 42 and the source line 43 for each of the writing, reading and erasing operations.

The comparison circuit 44 calculates the potential V of each bit line 42
BL1 to VBL2 are compared with a plurality of input information potentials VIN1 to VIN3 associated with storage information, and a decision output C1 is inverted when each bit line potential VBL1 to VBL3 exceeds each input information potential VIN1 to VIN3. ~ C3 are generated. The write / read control circuit 45 is connected to each of the bit lines 42, and controls the read clock φR and the comparison circuit 4
The power supply potential or the ground potential is supplied to the bit line 32 in response to the judgment outputs C1 to C3. Each write / read control circuit 45 corresponds to the read / write control circuit 35 of FIG.
After the initial setting by the reset clock φP, the power supply potential is supplied during the rise of the read clock φR, and when each of the judgment outputs C1 to C3 is at the high level during the fall, If the ground potential and the low level, the power supply potential is supplied.

Here, the input information potentials VIN1 to VIN3 are intermediate potentials between the ground potential and the power supply potential, respectively.
The operation when 1>VIN2> VIN3 will be described with reference to FIG. The write clock φW, the read clock φR, and the reset clock φP are the same as those in FIG. 2, and the write period (W) and the read period (R) are set while the reset clock φP is rising. When each memory cell transistor 40 is in the erased state, each of the bit line potentials VBL1 to VBL3 is a ground potential and is lower than each of the input information potentials VIN1 to VIN3.
All the judgment outputs C1 to C3 are at high level. Therefore,
Each write / read control circuit 45 is connected to each bit line 42
, A ground potential is supplied during the writing period.

When the write operation is repeated to increase the on-resistance of each memory cell transistor 30, as shown in FIG. 4, each bit line potential VBL1 in the read period is increased.
~ VBL3 gradually increases. The write operation is repeated. First, when the first bit line potential VBL1 exceeds the first input information potential VIN1, the judgment output C1 of the comparison circuit 44 is inverted, and the write operation to the memory cell transistor 40 in the first column is performed. Stop. At this point, the writing of the first input information potential VIN1 is completed. Subsequently, when the second bit line potential VBL2 exceeds the second input information potential VIN2, the judgment output C2 of the comparison circuit 44 is inverted, and the writing operation to the memory cell transistors 40 in the second column is stopped. At this point, the writing of the second input information potential VIN2 is completed. Then, when the third bit line potential VBL3 exceeds the third input information potential VIN3, the judgment output C3 of the comparison circuit 44 is inverted, and the writing operation to the third column memory cell transistor 40 is stopped. At this point, the writing of the third input information potential VIN3 is completed. In each column, after the writing is completed, the writing / writing is performed in the next writing period.
The power supply potential is supplied from the read control circuit 45 to the bit line 42.

In the above-described device, writing can be simultaneously performed on a plurality of memory cell transistors 40 on the same row, so that the time required for writing can be reduced.

[0029]

According to the present invention, the write operation to the memory cell transistor can be stopped by increasing the potential of the bit line while continuously supplying a high potential write clock. The reset clock for initializing the write / read control circuit is started at the memory cell selection operation, in other words, at the timing of address switching, and thus has a lower frequency and lower power consumption than the write clock and the read clock. .
Therefore, the circuit scale of the peripheral circuit necessary for writing and reading can be reduced.

In the case where a plurality of memory cell transistors are arranged, writing can be performed simultaneously on each memory cell transistor, and the time required for writing can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the nonvolatile semiconductor memory device of the present invention.

FIG. 4 is a timing chart for explaining the operation of the second embodiment.

FIG. 5 is a plan view showing a structure of a memory cell of a conventional nonvolatile semiconductor memory device.

FIG. 6 is a sectional view taken along line XX of FIG. 5;

FIG. 7 is a circuit diagram showing a configuration of a conventional nonvolatile semiconductor memory device.

FIG. 8 is a waveform diagram of a write clock and a read clock.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Isolation region 3, 5, 9 Oxide film 4 Floating gate 6 Control gate 7 Drain region 8 Source region 10 Aluminum wiring 11 Contact hole 20, 30, 40 Memory cell transistor 21, 31, 41 Word line 22, 32, 42 bit line 23, 33, 43 source line 24 selection transistor 25 data line 34, 44 comparison circuit 35, 45 read / write control circuit T1, T2, T3 transistor C1, C2 inverter A1 NAND gate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 16/00-16/34

Claims (3)

(57) [Claims] 1. A memory cell transistor having an electrically independent floating gate and changing an on-resistance value according to the amount of charge stored in the floating gate, and a memory cell transistor connected to a source side of the memory cell transistor. A source line, a bit line connected to the drain side of the memory cell transistor, and an input connected to the bit line, the potential of the bit line being associated with stored information.
A comparison circuit for comparing the potential with the force information potential ;
Is applied repeatedly and synchronized with the application of the first potential.
Charge from the bit line to the floating gate
Potential or the floating gate
While applying a third potential at which no charge can be injected into the
A write / read control circuit for causing a current to flow from the bit line to the source line via the memory cell transistor during a gap period between the application periods of the first potential, wherein the write / read control circuit comprises: After being initialized in synchronization with the selection operation of the transistor, a latch for latching the output of the comparison circuit, and in response to a clock having a constant cycle synchronized with a timing at which the first potential is applied to the source line. A first switch transistor for transmitting an output of the latch to the bit line, and a second switch transistor for connecting the bit line to a current supply in response to an inverted clock of the clock, Applying the second potential until the potential reaches the input information potential, and applying the third potential after reaching the determination potential The nonvolatile semiconductor memory device according to claim Rukoto. 2. A plurality of memory cell transistors having an electrically independent floating gate, and having a plurality of memory cell transistors arranged in a matrix for changing an on-resistance value according to an amount of electric charge stored in the floating gate, A source line commonly connected to the source side of the cell transistor;
A plurality of bit lines arranged corresponding to each column of the memory cell transistors and connected to the drain side of the memory cell transistors in the same column, and a plurality of bit lines connected to the plurality of bit lines, respectively. A plurality of comparator circuits for individually comparing each potential with a plurality of input information potentials associated with storage information; and a first cycle from the source line to the plurality of memory cell transistors at a constant period.
Is applied repeatedly and synchronized with the application of the first potential.
Then, when applied to the bit line, the floating
A second potential at which charge can be injected into the floating gate or
A third charge that cannot inject any charge into the loading gate
And a plurality of write / read control circuits for applying a potential and flowing a current from the plurality of bit lines to the source line via the plurality of memory cell transistors during a gap period of the application period of the first potential. A plurality of write / read control circuits, which are initialized in synchronization with a selection operation of the memory cell transistor, and then latch the output of the comparison circuit;
A first switch transistor for transmitting the output of the latch to the bit line in response to a clock having a constant period synchronized with the timing at which the potential is applied, and supplying a current to the bit line in response to an inverted clock of the clock. A second switch transistor connected to a source, the second potential being applied until the potentials of the plurality of bit lines reach the input information potential, and the third potential being applied after reaching the input information potential . A non-volatile semiconductor memory device characterized by applying the following potential: 3. A memory device further comprising a word line arranged corresponding to each row of the plurality of memory cell transistors and connected to a gate of each of the plurality of memory cell transistors, wherein a specific row is provided in response to row selection information. 3. The nonvolatile semiconductor memory device according to claim 2, wherein said memory cell transistor is selectively activated.