JPS59115538A - 集積回路の製造方法 - Google Patents
集積回路の製造方法Info
- Publication number
- JPS59115538A JPS59115538A JP58137952A JP13795283A JPS59115538A JP S59115538 A JPS59115538 A JP S59115538A JP 58137952 A JP58137952 A JP 58137952A JP 13795283 A JP13795283 A JP 13795283A JP S59115538 A JPS59115538 A JP S59115538A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- layer
- silicon dioxide
- isolation
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H10W10/13—
-
- H10P14/61—
-
- H10W10/0121—
Landscapes
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US450883 | 1982-12-20 | ||
| US06/450,883 US4508757A (en) | 1982-12-20 | 1982-12-20 | Method of manufacturing a minimum bird's beak recessed oxide isolation structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59115538A true JPS59115538A (ja) | 1984-07-04 |
| JPS6323656B2 JPS6323656B2 (enExample) | 1988-05-17 |
Family
ID=23789903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58137952A Granted JPS59115538A (ja) | 1982-12-20 | 1983-07-29 | 集積回路の製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4508757A (enExample) |
| EP (1) | EP0111774B1 (enExample) |
| JP (1) | JPS59115538A (enExample) |
| DE (1) | DE3372893D1 (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02132830A (ja) * | 1988-11-14 | 1990-05-22 | Sony Corp | 選択酸化方法 |
| US6239001B1 (en) | 1997-01-10 | 2001-05-29 | Nec Corporation | Method for making a semiconductor device |
Families Citing this family (42)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2579828A1 (fr) * | 1985-03-29 | 1986-10-03 | Thomson Csf | Procede d'oxydation localisee pour l'obtention d'oxyde epais |
| US4654269A (en) * | 1985-06-21 | 1987-03-31 | Fairchild Camera & Instrument Corp. | Stress relieved intermediate insulating layer for multilayer metalization |
| US4630356A (en) * | 1985-09-19 | 1986-12-23 | International Business Machines Corporation | Method of forming recessed oxide isolation with reduced steepness of the birds' neck |
| JPS62235776A (ja) * | 1986-04-04 | 1987-10-15 | Mitsubishi Electric Corp | 半導体集積回路装置の製造方法 |
| US4842675A (en) * | 1986-07-07 | 1989-06-27 | Texas Instruments Incorporated | Integrated circuit isolation process |
| US4892614A (en) * | 1986-07-07 | 1990-01-09 | Texas Instruments Incorporated | Integrated circuit isolation process |
| US5149669A (en) * | 1987-03-06 | 1992-09-22 | Seiko Instruments Inc. | Method of forming an isolation region in a semiconductor device |
| JPH01156418U (enExample) * | 1988-04-21 | 1989-10-27 | ||
| US5369051A (en) * | 1988-09-15 | 1994-11-29 | Texas Instruments Incorporated | Sidewall-sealed poly-buffered LOCOS isolation |
| US4897364A (en) * | 1989-02-27 | 1990-01-30 | Motorola, Inc. | Method for locos isolation using a framed oxidation mask and a polysilicon buffer layer |
| US5248350A (en) * | 1990-11-30 | 1993-09-28 | Ncr Corporation | Structure for improving gate oxide integrity for a semiconductor formed by a recessed sealed sidewall field oxidation process |
| US5192707A (en) * | 1991-07-31 | 1993-03-09 | Sgs-Thomson Microelectronics, Inc. | Method of forming isolated regions of oxide |
| KR940003070A (ko) * | 1992-07-10 | 1994-02-19 | 문정환 | 반도체소자의 단위소자간 격리방법 |
| KR950004972B1 (ko) * | 1992-10-13 | 1995-05-16 | 현대전자산업주식회사 | 반도체 장치의 필드산화막 형성 방법 |
| DE69434736D1 (de) * | 1993-08-31 | 2006-06-22 | St Microelectronics Inc | Isolationsstruktur und Verfahren zur Herstellung |
| US5927992A (en) * | 1993-12-22 | 1999-07-27 | Stmicroelectronics, Inc. | Method of forming a dielectric in an integrated circuit |
| US5543343A (en) * | 1993-12-22 | 1996-08-06 | Sgs-Thomson Microelectronics, Inc. | Method fabricating an integrated circuit |
| US5449638A (en) * | 1994-06-06 | 1995-09-12 | United Microelectronics Corporation | Process on thickness control for silicon-on-insulator technology |
| US5432118A (en) * | 1994-06-28 | 1995-07-11 | Motorola, Inc. | Process for forming field isolation |
| US5747357A (en) * | 1995-09-27 | 1998-05-05 | Mosel Vitelic, Inc. | Modified poly-buffered isolation |
| US5972776A (en) * | 1995-12-22 | 1999-10-26 | Stmicroelectronics, Inc. | Method of forming a planar isolation structure in an integrated circuit |
| US5834360A (en) * | 1996-07-31 | 1998-11-10 | Stmicroelectronics, Inc. | Method of forming an improved planar isolation structure in an integrated circuit |
| US6472244B1 (en) * | 1996-07-31 | 2002-10-29 | Sgs-Thomson Microelectronics S.R.L. | Manufacturing method and integrated microstructures of semiconductor material and integrated piezoresistive pressure sensor having a diaphragm of polycrystalline semiconductor material |
| US5843322A (en) * | 1996-12-23 | 1998-12-01 | Memc Electronic Materials, Inc. | Process for etching N, P, N+ and P+ type slugs and wafers |
| US6306727B1 (en) * | 1997-08-18 | 2001-10-23 | Micron Technology, Inc. | Advanced isolation process for large memory arrays |
| US5856003A (en) * | 1997-11-17 | 1999-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming pseudo buried layer for sub-micron bipolar or BiCMOS device |
| TW480643B (en) * | 2001-03-20 | 2002-03-21 | Mosel Vitelic Inc | Method for detecting metal on silicon chip by implantation of arsenic ions |
| US7518182B2 (en) | 2004-07-20 | 2009-04-14 | Micron Technology, Inc. | DRAM layout with vertical FETs and method of formation |
| US7247570B2 (en) | 2004-08-19 | 2007-07-24 | Micron Technology, Inc. | Silicon pillars for vertical transistors |
| US7285812B2 (en) | 2004-09-02 | 2007-10-23 | Micron Technology, Inc. | Vertical transistors |
| US7199419B2 (en) * | 2004-12-13 | 2007-04-03 | Micron Technology, Inc. | Memory structure for reduced floating body effect |
| US7229895B2 (en) * | 2005-01-14 | 2007-06-12 | Micron Technology, Inc | Memory array buried digit line |
| US7371627B1 (en) | 2005-05-13 | 2008-05-13 | Micron Technology, Inc. | Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines |
| US7120046B1 (en) | 2005-05-13 | 2006-10-10 | Micron Technology, Inc. | Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines |
| US7381631B2 (en) | 2005-07-05 | 2008-06-03 | Hewlett-Packard Development Company, L.P. | Use of expanding material oxides for nano-fabrication |
| US7888721B2 (en) | 2005-07-06 | 2011-02-15 | Micron Technology, Inc. | Surround gate access transistors with grown ultra-thin bodies |
| US7768051B2 (en) | 2005-07-25 | 2010-08-03 | Micron Technology, Inc. | DRAM including a vertical surround gate transistor |
| US7696567B2 (en) | 2005-08-31 | 2010-04-13 | Micron Technology, Inc | Semiconductor memory device |
| US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
| US9401363B2 (en) | 2011-08-23 | 2016-07-26 | Micron Technology, Inc. | Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices |
| KR102211607B1 (ko) * | 2013-03-28 | 2021-02-02 | 미쓰비시 마테리알 가부시키가이샤 | 실리콘 부재 및 실리콘 부재의 제조 방법 |
| US10163679B1 (en) * | 2017-05-31 | 2018-12-25 | Globalfoundries Inc. | Shallow trench isolation formation without planarization |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51142982A (en) * | 1975-05-05 | 1976-12-08 | Intel Corp | Method of producing single crystal silicon ic |
| JPS5840839A (ja) * | 1981-09-04 | 1983-03-09 | Toshiba Corp | 半導体装置の製造方法 |
| JPS5994843A (ja) * | 1982-11-24 | 1984-05-31 | Toshiba Corp | 半導体装置の製造方法 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL153374B (nl) * | 1966-10-05 | 1977-05-16 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze. |
| US3534234A (en) * | 1966-12-15 | 1970-10-13 | Texas Instruments Inc | Modified planar process for making semiconductor devices having ultrafine mesa type geometry |
| US3648125A (en) * | 1971-02-02 | 1972-03-07 | Fairchild Camera Instr Co | Method of fabricating integrated circuits with oxidized isolation and the resulting structure |
| NL7204741A (enExample) * | 1972-04-08 | 1973-10-10 | ||
| JPS547882A (en) * | 1977-06-21 | 1979-01-20 | Fujitsu Ltd | Manufacture for semiconductor device |
| US4373248A (en) * | 1978-07-12 | 1983-02-15 | Texas Instruments Incorporated | Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like |
| US4307180A (en) * | 1980-08-22 | 1981-12-22 | International Business Machines Corp. | Process of forming recessed dielectric regions in a monocrystalline silicon substrate |
| US4419142A (en) * | 1980-10-24 | 1983-12-06 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of forming dielectric isolation of device regions |
| DE3174638D1 (en) * | 1980-10-29 | 1986-06-19 | Fairchild Camera Instr Co | A method of fabricating a self-aligned integrated circuit structure using differential oxide growth |
| US4407696A (en) * | 1982-12-27 | 1983-10-04 | Mostek Corporation | Fabrication of isolation oxidation for MOS circuit |
-
1982
- 1982-12-20 US US06/450,883 patent/US4508757A/en not_active Expired - Lifetime
-
1983
- 1983-07-29 JP JP58137952A patent/JPS59115538A/ja active Granted
- 1983-11-24 DE DE8383111758T patent/DE3372893D1/de not_active Expired
- 1983-11-24 EP EP83111758A patent/EP0111774B1/en not_active Expired
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51142982A (en) * | 1975-05-05 | 1976-12-08 | Intel Corp | Method of producing single crystal silicon ic |
| JPS5840839A (ja) * | 1981-09-04 | 1983-03-09 | Toshiba Corp | 半導体装置の製造方法 |
| JPS5994843A (ja) * | 1982-11-24 | 1984-05-31 | Toshiba Corp | 半導体装置の製造方法 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02132830A (ja) * | 1988-11-14 | 1990-05-22 | Sony Corp | 選択酸化方法 |
| US6239001B1 (en) | 1997-01-10 | 2001-05-29 | Nec Corporation | Method for making a semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0111774A1 (en) | 1984-06-27 |
| US4508757A (en) | 1985-04-02 |
| DE3372893D1 (en) | 1987-09-10 |
| JPS6323656B2 (enExample) | 1988-05-17 |
| EP0111774B1 (en) | 1987-08-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS59115538A (ja) | 集積回路の製造方法 | |
| US5151381A (en) | Method for local oxidation of silicon employing two oxidation steps | |
| JP3058954B2 (ja) | 絶縁層の上に成長層を有する半導体装置の製造方法 | |
| US4493740A (en) | Method for formation of isolation oxide regions in semiconductor substrates | |
| EP0036111A2 (en) | Method for making fine deep dielectric isolation | |
| JPS6340337A (ja) | 集積回路分離法 | |
| JPH0461494B2 (enExample) | ||
| GB2156149A (en) | Dielectrically-isolated integrated circuit manufacture | |
| US4398992A (en) | Defect free zero oxide encroachment process for semiconductor fabrication | |
| US4408387A (en) | Method for producing a bipolar transistor utilizing an oxidized semiconductor masking layer in conjunction with an anti-oxidation mask | |
| KR940009361B1 (ko) | 복합형 직접회로소자 | |
| EP0071203A2 (en) | Mask for thermal oxidation and method of forming dielectric isolation surrounding regions | |
| US4088516A (en) | Method of manufacturing a semiconductor device | |
| US6033991A (en) | Isolation scheme based on recessed locos using a sloped Si etch and dry field oxidation | |
| US5256563A (en) | Doped well structure and method for semiconductor technologies | |
| JP2989051B2 (ja) | 炭化シリコンバイポーラ半導体装置およびその製造方法 | |
| EP0239384B1 (en) | Process for isolating semiconductor devices on a substrate | |
| EP0140749A1 (en) | Method for producing a complementary semiconductor device with a dielectric isolation structure | |
| US4546537A (en) | Method for producing a semiconductor device utilizing V-groove etching and thermal oxidation | |
| JPS5992547A (ja) | アイソレ−シヨン方法 | |
| JPS59208744A (ja) | 半導体装置 | |
| JPS59188936A (ja) | 半導体装置の製造方法 | |
| JPS6322065B2 (enExample) | ||
| JPS63141346A (ja) | 半導体装置の製造方法 | |
| KR940009578B1 (ko) | 반도체 장치 및 그 제조방법 |