JPS59115538A - 集積回路の製造方法 - Google Patents

集積回路の製造方法

Info

Publication number
JPS59115538A
JPS59115538A JP58137952A JP13795283A JPS59115538A JP S59115538 A JPS59115538 A JP S59115538A JP 58137952 A JP58137952 A JP 58137952A JP 13795283 A JP13795283 A JP 13795283A JP S59115538 A JPS59115538 A JP S59115538A
Authority
JP
Japan
Prior art keywords
silicon
layer
silicon dioxide
isolation
silicon nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58137952A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6323656B2 (enExample
Inventor
カレン・アン・フアブリシヤス
バ−ナ−ド・マイケル・ケムレ−ジ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS59115538A publication Critical patent/JPS59115538A/ja
Publication of JPS6323656B2 publication Critical patent/JPS6323656B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
JP58137952A 1982-12-20 1983-07-29 集積回路の製造方法 Granted JPS59115538A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/450,883 US4508757A (en) 1982-12-20 1982-12-20 Method of manufacturing a minimum bird's beak recessed oxide isolation structure
US450883 1989-12-14

Publications (2)

Publication Number Publication Date
JPS59115538A true JPS59115538A (ja) 1984-07-04
JPS6323656B2 JPS6323656B2 (enExample) 1988-05-17

Family

ID=23789903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58137952A Granted JPS59115538A (ja) 1982-12-20 1983-07-29 集積回路の製造方法

Country Status (4)

Country Link
US (1) US4508757A (enExample)
EP (1) EP0111774B1 (enExample)
JP (1) JPS59115538A (enExample)
DE (1) DE3372893D1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02132830A (ja) * 1988-11-14 1990-05-22 Sony Corp 選択酸化方法
US6239001B1 (en) 1997-01-10 2001-05-29 Nec Corporation Method for making a semiconductor device

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2579828A1 (fr) * 1985-03-29 1986-10-03 Thomson Csf Procede d'oxydation localisee pour l'obtention d'oxyde epais
US4654269A (en) * 1985-06-21 1987-03-31 Fairchild Camera & Instrument Corp. Stress relieved intermediate insulating layer for multilayer metalization
US4630356A (en) * 1985-09-19 1986-12-23 International Business Machines Corporation Method of forming recessed oxide isolation with reduced steepness of the birds' neck
JPS62235776A (ja) * 1986-04-04 1987-10-15 Mitsubishi Electric Corp 半導体集積回路装置の製造方法
US4842675A (en) * 1986-07-07 1989-06-27 Texas Instruments Incorporated Integrated circuit isolation process
US4892614A (en) * 1986-07-07 1990-01-09 Texas Instruments Incorporated Integrated circuit isolation process
US5149669A (en) * 1987-03-06 1992-09-22 Seiko Instruments Inc. Method of forming an isolation region in a semiconductor device
JPH01156418U (enExample) * 1988-04-21 1989-10-27
US5369051A (en) * 1988-09-15 1994-11-29 Texas Instruments Incorporated Sidewall-sealed poly-buffered LOCOS isolation
US4897364A (en) * 1989-02-27 1990-01-30 Motorola, Inc. Method for locos isolation using a framed oxidation mask and a polysilicon buffer layer
US5248350A (en) * 1990-11-30 1993-09-28 Ncr Corporation Structure for improving gate oxide integrity for a semiconductor formed by a recessed sealed sidewall field oxidation process
US5192707A (en) * 1991-07-31 1993-03-09 Sgs-Thomson Microelectronics, Inc. Method of forming isolated regions of oxide
KR940003070A (ko) * 1992-07-10 1994-02-19 문정환 반도체소자의 단위소자간 격리방법
KR950004972B1 (ko) * 1992-10-13 1995-05-16 현대전자산업주식회사 반도체 장치의 필드산화막 형성 방법
EP0641022B1 (en) * 1993-08-31 2006-05-17 STMicroelectronics, Inc. Isolation structure and method for making same
US5543343A (en) * 1993-12-22 1996-08-06 Sgs-Thomson Microelectronics, Inc. Method fabricating an integrated circuit
US5927992A (en) * 1993-12-22 1999-07-27 Stmicroelectronics, Inc. Method of forming a dielectric in an integrated circuit
US5449638A (en) * 1994-06-06 1995-09-12 United Microelectronics Corporation Process on thickness control for silicon-on-insulator technology
US5432118A (en) * 1994-06-28 1995-07-11 Motorola, Inc. Process for forming field isolation
US5747357A (en) 1995-09-27 1998-05-05 Mosel Vitelic, Inc. Modified poly-buffered isolation
US5972776A (en) * 1995-12-22 1999-10-26 Stmicroelectronics, Inc. Method of forming a planar isolation structure in an integrated circuit
US5834360A (en) * 1996-07-31 1998-11-10 Stmicroelectronics, Inc. Method of forming an improved planar isolation structure in an integrated circuit
US6472244B1 (en) * 1996-07-31 2002-10-29 Sgs-Thomson Microelectronics S.R.L. Manufacturing method and integrated microstructures of semiconductor material and integrated piezoresistive pressure sensor having a diaphragm of polycrystalline semiconductor material
US5843322A (en) * 1996-12-23 1998-12-01 Memc Electronic Materials, Inc. Process for etching N, P, N+ and P+ type slugs and wafers
US6306727B1 (en) * 1997-08-18 2001-10-23 Micron Technology, Inc. Advanced isolation process for large memory arrays
US5856003A (en) * 1997-11-17 1999-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming pseudo buried layer for sub-micron bipolar or BiCMOS device
TW480643B (en) * 2001-03-20 2002-03-21 Mosel Vitelic Inc Method for detecting metal on silicon chip by implantation of arsenic ions
US7518182B2 (en) 2004-07-20 2009-04-14 Micron Technology, Inc. DRAM layout with vertical FETs and method of formation
US7247570B2 (en) * 2004-08-19 2007-07-24 Micron Technology, Inc. Silicon pillars for vertical transistors
US7285812B2 (en) * 2004-09-02 2007-10-23 Micron Technology, Inc. Vertical transistors
US7199419B2 (en) * 2004-12-13 2007-04-03 Micron Technology, Inc. Memory structure for reduced floating body effect
US7229895B2 (en) * 2005-01-14 2007-06-12 Micron Technology, Inc Memory array buried digit line
US7371627B1 (en) 2005-05-13 2008-05-13 Micron Technology, Inc. Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
US7120046B1 (en) * 2005-05-13 2006-10-10 Micron Technology, Inc. Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
US7381631B2 (en) * 2005-07-05 2008-06-03 Hewlett-Packard Development Company, L.P. Use of expanding material oxides for nano-fabrication
US7888721B2 (en) 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US9401363B2 (en) 2011-08-23 2016-07-26 Micron Technology, Inc. Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices
TWI602779B (zh) * 2013-03-28 2017-10-21 三菱綜合材料股份有限公司 矽構材及矽構材之製造方法
US10163679B1 (en) * 2017-05-31 2018-12-25 Globalfoundries Inc. Shallow trench isolation formation without planarization

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51142982A (en) * 1975-05-05 1976-12-08 Intel Corp Method of producing single crystal silicon ic
JPS5840839A (ja) * 1981-09-04 1983-03-09 Toshiba Corp 半導体装置の製造方法
JPS5994843A (ja) * 1982-11-24 1984-05-31 Toshiba Corp 半導体装置の製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL153374B (nl) * 1966-10-05 1977-05-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze.
US3534234A (en) * 1966-12-15 1970-10-13 Texas Instruments Inc Modified planar process for making semiconductor devices having ultrafine mesa type geometry
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
NL7204741A (enExample) * 1972-04-08 1973-10-10
JPS547882A (en) * 1977-06-21 1979-01-20 Fujitsu Ltd Manufacture for semiconductor device
US4373248A (en) * 1978-07-12 1983-02-15 Texas Instruments Incorporated Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like
US4307180A (en) * 1980-08-22 1981-12-22 International Business Machines Corp. Process of forming recessed dielectric regions in a monocrystalline silicon substrate
US4419142A (en) * 1980-10-24 1983-12-06 Tokyo Shibaura Denki Kabushiki Kaisha Method of forming dielectric isolation of device regions
EP0051534B1 (en) * 1980-10-29 1986-05-14 FAIRCHILD CAMERA & INSTRUMENT CORPORATION A method of fabricating a self-aligned integrated circuit structure using differential oxide growth
US4407696A (en) * 1982-12-27 1983-10-04 Mostek Corporation Fabrication of isolation oxidation for MOS circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51142982A (en) * 1975-05-05 1976-12-08 Intel Corp Method of producing single crystal silicon ic
JPS5840839A (ja) * 1981-09-04 1983-03-09 Toshiba Corp 半導体装置の製造方法
JPS5994843A (ja) * 1982-11-24 1984-05-31 Toshiba Corp 半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02132830A (ja) * 1988-11-14 1990-05-22 Sony Corp 選択酸化方法
US6239001B1 (en) 1997-01-10 2001-05-29 Nec Corporation Method for making a semiconductor device

Also Published As

Publication number Publication date
US4508757A (en) 1985-04-02
EP0111774A1 (en) 1984-06-27
JPS6323656B2 (enExample) 1988-05-17
EP0111774B1 (en) 1987-08-05
DE3372893D1 (en) 1987-09-10

Similar Documents

Publication Publication Date Title
JPS59115538A (ja) 集積回路の製造方法
US5151381A (en) Method for local oxidation of silicon employing two oxidation steps
JP3058954B2 (ja) 絶縁層の上に成長層を有する半導体装置の製造方法
EP0036111B1 (en) Method for making fine deep dielectric isolation
US4493740A (en) Method for formation of isolation oxide regions in semiconductor substrates
JPS6340337A (ja) 集積回路分離法
JPH0461494B2 (enExample)
GB2156149A (en) Dielectrically-isolated integrated circuit manufacture
US4398992A (en) Defect free zero oxide encroachment process for semiconductor fabrication
US4408387A (en) Method for producing a bipolar transistor utilizing an oxidized semiconductor masking layer in conjunction with an anti-oxidation mask
KR940009361B1 (ko) 복합형 직접회로소자
JPH02222161A (ja) 半導体装置の製造方法
EP0071203A2 (en) Mask for thermal oxidation and method of forming dielectric isolation surrounding regions
US4088516A (en) Method of manufacturing a semiconductor device
US6033991A (en) Isolation scheme based on recessed locos using a sloped Si etch and dry field oxidation
US5256563A (en) Doped well structure and method for semiconductor technologies
JP2989051B2 (ja) 炭化シリコンバイポーラ半導体装置およびその製造方法
EP0239384B1 (en) Process for isolating semiconductor devices on a substrate
US4231819A (en) Dielectric isolation method using shallow oxide and polycrystalline silicon utilizing a preliminary etching step
EP0140749A1 (en) Method for producing a complementary semiconductor device with a dielectric isolation structure
US4546537A (en) Method for producing a semiconductor device utilizing V-groove etching and thermal oxidation
JPS5992547A (ja) アイソレ−シヨン方法
JPS59208744A (ja) 半導体装置
JPS6322065B2 (enExample)
JPS59188936A (ja) 半導体装置の製造方法