JPS59112351A - メモリ装置制御方式 - Google Patents

メモリ装置制御方式

Info

Publication number
JPS59112351A
JPS59112351A JP57223470A JP22347082A JPS59112351A JP S59112351 A JPS59112351 A JP S59112351A JP 57223470 A JP57223470 A JP 57223470A JP 22347082 A JP22347082 A JP 22347082A JP S59112351 A JPS59112351 A JP S59112351A
Authority
JP
Japan
Prior art keywords
memory
address
memory device
access
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57223470A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0370816B2 (enrdf_load_stackoverflow
Inventor
Osamu Miura
修 三浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57223470A priority Critical patent/JPS59112351A/ja
Publication of JPS59112351A publication Critical patent/JPS59112351A/ja
Publication of JPH0370816B2 publication Critical patent/JPH0370816B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Multi Processors (AREA)
JP57223470A 1982-12-20 1982-12-20 メモリ装置制御方式 Granted JPS59112351A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57223470A JPS59112351A (ja) 1982-12-20 1982-12-20 メモリ装置制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57223470A JPS59112351A (ja) 1982-12-20 1982-12-20 メモリ装置制御方式

Publications (2)

Publication Number Publication Date
JPS59112351A true JPS59112351A (ja) 1984-06-28
JPH0370816B2 JPH0370816B2 (enrdf_load_stackoverflow) 1991-11-11

Family

ID=16798638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57223470A Granted JPS59112351A (ja) 1982-12-20 1982-12-20 メモリ装置制御方式

Country Status (1)

Country Link
JP (1) JPS59112351A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0573470A (ja) * 1991-09-12 1993-03-26 Nec Corp デユアル・ポート記憶装置
JPH06214871A (ja) * 1992-12-04 1994-08-05 Internatl Business Mach Corp <Ibm> デュアルポート電子データ記憶システム及び電子データ記憶システム、並びに同時アクセス方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0573470A (ja) * 1991-09-12 1993-03-26 Nec Corp デユアル・ポート記憶装置
JPH06214871A (ja) * 1992-12-04 1994-08-05 Internatl Business Mach Corp <Ibm> デュアルポート電子データ記憶システム及び電子データ記憶システム、並びに同時アクセス方法

Also Published As

Publication number Publication date
JPH0370816B2 (enrdf_load_stackoverflow) 1991-11-11

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