JPS59112351A - Controlling system of memory device - Google Patents

Abstract

PURPOSE:To shorten processing time without generating waiting at a common memory device in case of observing from the controlling device side even if accesses to the common memory device collide with each other, by providing a memory access switching control means. CONSTITUTION:Controlling devices PRCB 11, PRCA 10 access memory devices MEM1 21, MEM0 20 in parallel through a memory access switching controlling device MCNT 30. Namely, control signals C1, C0 access the reading of data D1 and the writing of data D0 of addresses specified by access address signals A1, A0 and the signal A0 is stored in an address register REG 300. A controlling part 301 specifies the reading to the MEM0 20 and writing to the MEM1 21 by control signals and the REG 300 transmits the signal A0. Consequently, the data D0 of the address specified by the signal A0 and written in the same address in the MEM1 21. Thus, the processing time can be shortened without generating waiting time.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a memory device control method, and particularly to a memory device control method in an information transfer method in which C information is transferred via two memory devices common to two control devices. Regarding the method.

[Conventional technology and problems]

Conventionally, in this type of information transfer method, when accesses from two control devices to a common memory device collide, these memory accesses are prioritized, and the control device with non-priority access ends the processing of the control device with priority access. A memory device control method is adopted in which processing is performed by waiting until the end of the process.

However, this method has the drawback that when real-time processing is required, not only is it impossible to satisfy the bill due to this waiting time, but also the total processing time of both control devices becomes long.

[Purpose of the invention]

An object of the present invention is to provide a memory device control method that eliminates the above-mentioned drawbacks by providing memory access switching control means, and prevents queuing in a common memory device from the viewpoint of the tlj control device even when accesses collide. Our goal is to provide the following.

[Summary of the invention]

A memory device control method according to the present invention is an information transfer method in which information is transferred via two memory devices common to two control devices, and when one control device performs information write access to the two memory devices. Then, when the other control device is not accessing any of the memory devices, the same address of the two memory devices is written with sympathy @ all write 1, and when the other control device is accessing the dominant memory device. When the information is written to the other memory device, the write address is temporarily stored, and when the accesses of both the control devices are completed, the information of the address of the other memory device is written to the one memory device. The present invention is characterized in that it includes a memory access switching control means for controlling the access to the address. Further, the memory access switching control means is characterized in that it includes a register that temporarily stores a write address, and a control section that monitors the memory access state and controls information transfer between memory devices.

[Embodiments of the invention]

Next, the present invention will be explained with reference to the drawings.

FIGS. 1, 2(a) and 2(b) are block diagrams showing an embodiment of the memory device control method of the present invention. When writing information from one control device to two memory devices, Figure 1 shows the flow of information (signals and data) when the other control device is not accessing either memory device, that is, when there is no access conflict, and Figure 1 shows the flow of information when there is an access conflict. Figure 2 (a),
Shown in (b). In either case, information transfer is carried out between two control devices (PaC) PRCAIO and PRCBII, and the PRC memory access switching control device (MCNT).
) 30. Note that the MCNT 30 corresponds to memory access switching control means described in the claims.

In FIG. 1, PRCAIO connects MCN'l"30 to
A control signal co is sent to 21 for access and to issue a write instruction. Subsequently, since the address signal Ao and data Do are transmitted from the PR and CA10, the M
Nuclear address signal A in EMo20 and MEM, 21.

The same data Do is written to the same address indicated by.

Moreover, in FIG. 2(a), PaCBlt is MCN'
Sends a control signal C, to MEM, 21 via r30.
C is accessed and the address indicated by the address signal A is being read.
access behavior). In parallel with the access operation, PRC
The AIO accesses the MEMO 20 via the MCNT 30 using the open side signal co, and writes data D to the address indicated by the address signal Ao. The address signal Ao (write address) & is also stored in the address register (hereinafter referred to as REG) 300 (access operation of PRCAIO).

When both the PRCAxO and PRCBll access operations are completed, the M
CN T 30 ”'C is the control unit (hereinafter referred to as CNT) 301
After recognizing this, said MEM, 20 and MEM
+21. For example, the control signals C1 and co are transmitted to the MEM 20 and the MEM 121 are instructed to read, and the MEM 121 is instructed to write.
EMo202MEM+ 21 to Mi said address signal A
o, so the address signal A of the MEM, 20
The data Do at the address (read address) indicated by o is read out and written to the same address (write address) #MEM, 21.

In addition, in Fig. 2 (a), PRCAI O, PRCBL 1
exemplified the case where MEMo 20, MEM, and 21 are accessed, respectively, but the flow of information and operation in other cases are the same as those described above.

Next, FIG. 3 is a circuit diagram showing an example of the main parts of the memory access switching control device in FIGS. 1, 2(a) and 2(b), and the same components are given the same reference numerals. be. In the same figure, the MCNT 30 constitutes an R and an EG 300 that temporarily store storage addresses, and a CNT 301 (shown in FIG. 2(b)) that monitors the memory access state and controls information transfer between the MEMO 20, MEM, and 21. Flip-flop (hereinafter referred to as F/F) 302. A timing circuit (hereinafter referred to as TM) 303 and related gate circuits, and P
RCAI O.

PL (, CBII and the MEMo20, MEM, 21
It includes related gate circuits that transfer control signals, address signals, and data between the two.

Memory read data (hereinafter referred to as R, D) from MEMo 20 and MEMI 21 is connected to read data (hereinafter referred to as RDA, RDB) through AND gates (hereinafter referred to as AND) 310 and 321, respectively.
Transferred to BII, write data (hereinafter WDA) from #PRcAlo, read/write control signal (hereinafter) L/
WA), access signal (hereinafter referred to as C8A) and address signal (hereinafter referred to as ADRA) are ANi) 311 and 312, respectively.
．． ORGATE (hereinafter referred to as 0)1. ) 340 and AND
Memory write data (hereinafter referred to as WD) and memory read/write control signal (hereinafter referred to as R/W) through 0R313 and 0R341.
, is transferred to the MEMo20 as a memory access signal (hereinafter referred to as C8) and a memory address signal (hereinafter referred to as ADR), and is transferred to the MEMo20 as a memory access signal (hereinafter referred to as C8) and a memory address signal (hereinafter referred to as ADR), and is transferred to the MEMo20 as an address signal (hereinafter referred to as ADf) from the PRCBII.
(,B) and the access signal (hereinafter referred to as CS B) are AND 320 and oaa 42., respectively. and through the WDA and AND318 (~ the MEM
The RD from O20 passes through oa345 to the ME
M, 21 memory write data WD is transferred as the t(,/WA is 0R34) via the AND312.
A memory read/write control signal R/W is applied to the MEM 121 via ANL) 317, and the AD)LA is input to the OR 342 via ANL) 317. Furthermore, the C8
A is the above AND) 310.

311.312, and the C8B is the AND
321 and performs gate control respectively, and A
When the C8A, C, and SB occur simultaneously, the AND condition is satisfied, and the ND314 applies a signal to the S terminal of the F/F 302 to set the F'/F 302, and the AN
A signal is given to the CK terminal of the R and EG300 through the D313 to store the A I) f(A, ANI)3
15 is an inverter (hereinafter referred to as IN V) 331
, 332e 1,7v said C8A.

AND the inverted signal of C8B and the output of F/F302, and T
Give a start signal (hereinafter referred to as ST) to M303, AND31.
6 ANDs 1C8A and the inverted signal of C8B via INV333 and becomes the input of the AND317 to perform gate control, and also provides the C9-8 to the MEM+21 via the (11, 343). The TM303 receives the ST and generates and outputs a predetermined gate signal (hereinafter referred to as GT), a write signal (hereinafter referred to as WR), and a reset signal (hereinafter referred to as R8).The GT is input to the AND318 and AND319, and is connected to the C gate. In addition to performing control, each of the above 0
．． 11,340, the MEMo20 via 3'43
, MEM+ 21, and the inverted signal of the GT via INV330 becomes an input to the AND313 to perform gate control. The WR gives a write instruction to the MEM 121 via the OR 344, and the R8 is given to the R/T terminal of the F/F 302 to read the F/F'
302 is reset. Furthermore, the AND 319 selects the memory contents of the R, EG 300 (, vil
:inclusive address) is outputted from the Qn terminal of the EG 300 and C gives an address instruction to the MEMo 20, MEM, and 21 via the 0Rs 341 and 342, respectively.

In FIG. 3, address signal and data transfer related gate circuits, ie, AND310°-10=311.313,317. ~321. 0 几341゜3
42 and 345 are each composed of a plurality of gates, and all the components of the MCNT 30 including the TM 303 can be easily realized using conventional technology.

Next, FIG. 4 is a time chart of various signals related to the timing circuit in FIG. 3, with reference symbols C8A,
C8B, ST, GT, WR and R8 correspond to those shown in FIG. 3, respectively. In the same figure, PRC
When the memory accesses of AIO and PRCBI 1 (both shown in FIG. 3) collide and each access operation ends, that is, when C8A and C8B become rOJ, ST becomes 11'' and TM303 (see FIG. 3). ) is started. The TM303 outputs "1" to GT, and after a predetermined timing 1o, outputs "1" to WR, and
The EMr 21 (shown in FIG. 3) is caused to write data. Then, after a predetermined timing 1o, the TM 303 outputs "1" to the box S, sets the ST, GT and WR to 10, resets the F/F'302 (shown in FIG. 3), and then outputs "1" to the box S. 10". Note that the timing to.

tl may be arbitrarily determined depending on the access time of each memory device.

Next, the operation of this embodiment will be described in detail with reference to FIG.

P)? , CAI O, and PRCB 11 do not conflict, AND313 and 316 are INV
330.333 Turned on by output "1".

When the PRCAIO sets C8A to “1”, AND3
11, 312 and 317 are turned on and M E Mo 20 through 0R340, 343 respectively,
C8 of M E M + 21 becomes “1” and the PR
CA10 accesses nuclear MEM. Said PRCAI
When O sets the write control signal WA to 11'', the AND
312 output sets the memory write control signal (hereinafter referred to as W) of the MEMo20 to "11" and sets the W of the MEM and 21 to "1" via 0ft344, so the MEM in the nucleus
A write instruction is given to the AN, and ADH and A are respectively written to the AN.
D313,0 341 and AND317,0 342
ADR of MEMO20 and MEMI21 via
will be transferred as In addition, the WDA from Mayuki P 几 CAl0 via the AND311 is transferred as the WD of the MEMo20, and is also transferred to the MEMo via 0R4345.
It is transferred as a WD of Mt21. Therefore, the said P
Write data from IQ is simultaneously written to the same address of both MEMs.

Next, when accesses collide, for example, while PftCBll is reading MEM+21 and accessing it, PRCAlo is accessing MEM+21.
When writing data to EM, the PRCB11 and ME
A generally known data read operation is performed between M and 21. That is, by setting C8B to ``1'', C8 is set to 1゛1'' via 0R343, and KAND320゜321 is turned on, and the read control signal R
By setting B to "1", the memory read control signal R is set to "1", and the ADRDB AND320.0R342
Since the MEM113 is transferred as ADR via
-21 predetermined addresses are read out as RDB via the AND 321. During this read access operation, the CAB is "1", so the AND314
is on, AND 316 is turned off by INv333 output rOJ, and AND315 is given ■Nv332 output "0". On the other hand, the P 几 CAl0 and M
Between the E Mo 20, WD is written to a predetermined address of the MEMo 20 in the same manner as in the case where there is no access conflict, and ADRA is AND3
13 to the D0 terminal of the EG300 and the corresponding RB
G300, but the AND 316 therefore A
Since ND 317 is in the off state, the MEM.

Memory write address transfer to 21 is not performed.

Since C8A is "1", the AND315 is turned off by the output "0" of the Nv331, and the F/F 302 is set by the output "1" of the AND314, and the output "1" of the F/F 302 is set. A, given in ND315. Then, the PFLCAI O, Pf
When the access operation 14- of the LCB 11 is completed, the C8A and C8B become rOJ, so the AND315 is turned on and the TM303 is activated. When the GT from the TM303 becomes 11'', each becomes O 340. Both MEs via the 0ft343
C8 of M becomes "1", and the above AND313UIN
Since it is turned off by the V330 output "0", the PRC
Even if there is an input of ADf (, A) from AIO, it is blocked, and the stored contents (address signal) of R, EG 300 are transmitted through AND 319 turned on by GT, and further through 0aa4i and Of, 342, respectively. Both M
Transferred to EM as ADR. Wft from the 'rM303 is given to the MEM 21 as a memory write control signal W via the 0R344. Therefore, the MEM
o20's predetermined address f(D is transferred as the WD of the MEM121 through the AND 318 and 0R345 turned on by the GT and written to the predetermined address. When this write operation is completed, the TM303
sets R8 to "1" and resets the F/F 302.

Note that AND310 is a gate circuit used when PCA10 reads and accesses MEMo20, and AND3
Since it is the same as No. 21, detailed explanation will be omitted.

〔Effect of the invention〕

As is clear from the above description, according to the memory device control method of the present invention, by providing the memory access switching control means, even when there is a conflict in accesses to the common memory device, the common memory device is Since no queuing occurs, real-time processing requests can be satisfied and the total processing time of both control devices can be significantly shortened.

[Brief explanation of the drawing]

FIGS. 1 and 2 (a) and 2 (b) are block diagrams showing one embodiment of the memory device control method of the present invention, and FIG.
2(a) and 2(b) are circuit diagrams showing an example of the main parts of the memory access switching control device, and FIG. 4 is a time chart of various signals related to the timing circuit in FIG. 3. In the figure, %10111...Control device PRCA
. PRCB, 20.21...-Memory unit [MEMo. MBM, 30...Memory access switching control device MCNT, 300...Address register BE
G. 301...Control unit CN'l', 302...
...Flip-flop F/F, 303...Timing circuit TM. 310, ~321...and gate, 33o,
~333゛°°・°・Inverter, 340. ~345・
...or gate. -17 to

Claims (1)

[Claims] (1) An information transfer method in which information is transferred via two memory devices that are common to two control devices.C1 When one control device performs information write access to the two memory devices, the other When the control device is not accessing either memory device, the same information is written to the same address of the two memory devices, and when the other control device is accessing one memory device, the same information is written to the other memory device. When the information is written to the memory device, the write address is temporarily stored, and when the accesses of both the control devices are completed, the information of the address of the other memory device is written to the address of the one memory device. 1. A memory device control method, comprising: memory access switching control means. (2. In the memory device control method described in claim (1), the memory access switching control means includes a register that temporarily stores the write address, monitors the memory access state, and controls information transfer between the memory devices. A memory device control method comprising a control unit.