JPS5898938A - 半導体集積回路 - Google Patents

半導体集積回路

Info

Publication number
JPS5898938A
JPS5898938A JP56197828A JP19782881A JPS5898938A JP S5898938 A JPS5898938 A JP S5898938A JP 56197828 A JP56197828 A JP 56197828A JP 19782881 A JP19782881 A JP 19782881A JP S5898938 A JPS5898938 A JP S5898938A
Authority
JP
Japan
Prior art keywords
pad
semiconductor integrated
integrated circuit
insulator
distance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56197828A
Other languages
English (en)
Inventor
Yasushi Kawakami
靖 川上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56197828A priority Critical patent/JPS5898938A/ja
Publication of JPS5898938A publication Critical patent/JPS5898938A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は、特に半導体集積回路装置におけるポンディン
グパッド部の構造に関する。
最近、半導体集積回路は、益々その集積度を増している
が、ボンディング用のパッドの大きさ、ノくラド間隔、
パッドと内部素子との距離が、半導体集積回路のチーノ
ブサイズに大きな影響をおよぼしている。
本発明は、パッドの面からチップナイズの縮少化につな
がる方法を提供するものである。
以下、図面により本発明の詳細な説明する。
第１図は、通常の半導体集積回動の部分平面図であり、
ｌはシリコン基板、２は金属パッド、３は内部素子が形
成査れる境界又は内部配線、４はパッドから内部素子ま
での距離を示す。このパ。
ド２と内部素子３までの距離は一定間隔離さねばならな
い。そこで、本発明はこの距離をより短くするものであ
る。すなわち、第２，３図のようにパッドを二重構造に
することで、内部素子とパッド５の距離を最少にするこ
とが可能である。第３図の５を第１パツド、２１を第２
パツドとすると、絶縁物カバーの形成時に、第１パツド
５の上に穴があくように絶縁物６でカバーし、次に第２
パ。
ドな蒸着させて再び絶縁物６でカバーする。このようＫ
することで、第１パツド５と内部素子３との距離７を最
小で設計できるため、集積度な上げることが可能である
。また、ボンディングに必要な面積はパッド２′で得て
いる。第３図かられかるようにパッド２１と素子３との
距離は平面的にみてほとんどない。
このように内部素子との入出力を行うパッドと外部との
接続を行うパッドを有する構造のものはすべて含まれる
。
【図面の簡単な説明】
第１図は、従来の半導体集積回路のチップの部分平面図
であり、第２図は、本発明の一実施例の部分平面図であ
り、第３図は第２図の断面図である。

Claims (1)

    【特許請求の範囲】
  1. 半導体装置のボンディング用のパッドにおいて内部素子
    との入出力をやりとりするパッドと、ボンディング用の
    パッドを有し二重構造を成す半導体集積回動。
JP56197828A 1981-12-09 1981-12-09 半導体集積回路 Pending JPS5898938A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56197828A JPS5898938A (ja) 1981-12-09 1981-12-09 半導体集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56197828A JPS5898938A (ja) 1981-12-09 1981-12-09 半導体集積回路

Publications (1)

Publication Number Publication Date
JPS5898938A true JPS5898938A (ja) 1983-06-13

Family

ID=16381010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56197828A Pending JPS5898938A (ja) 1981-12-09 1981-12-09 半導体集積回路

Country Status (1)

Country Link
JP (1) JPS5898938A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4688070A (en) * 1983-05-24 1987-08-18 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device
EP0693782A1 (en) * 1994-07-13 1996-01-24 United Microelectronics Corporation Method for reducing process antenna effect
US5891745A (en) * 1994-10-28 1999-04-06 Honeywell Inc. Test and tear-away bond pad design

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4688070A (en) * 1983-05-24 1987-08-18 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device
EP0693782A1 (en) * 1994-07-13 1996-01-24 United Microelectronics Corporation Method for reducing process antenna effect
US5891745A (en) * 1994-10-28 1999-04-06 Honeywell Inc. Test and tear-away bond pad design

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