JPS59146967U - セラミツク配線基板 - Google Patents

セラミツク配線基板

Info

Publication number
JPS59146967U
JPS59146967U JP1983040603U JP4060383U JPS59146967U JP S59146967 U JPS59146967 U JP S59146967U JP 1983040603 U JP1983040603 U JP 1983040603U JP 4060383 U JP4060383 U JP 4060383U JP S59146967 U JPS59146967 U JP S59146967U
Authority
JP
Japan
Prior art keywords
wiring board
wiring pattern
ceramic wiring
chip connection
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983040603U
Other languages
English (en)
Inventor
草野　正昭
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP1983040603U priority Critical patent/JPS59146967U/ja
Publication of JPS59146967U publication Critical patent/JPS59146967U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/11013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bump connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図及び第２図は従来のフェースダウン接続形集積回
路の断面図及び平面図、第３図は本考案の第１の実施例
を示す平面図、第４図はその部分拡大図、第５図は本考
案の他の実施例を示す平面図、第６図はその部分拡大図
である。 １２．２２・・・・・・配線パターン、１３・・・・・
・絶縁層パターン、１４．２４・・・・・・チップ接続
部、１５゜２５・・・・・・チップ、２３・・・・・・
絶縁層の窓。 第　３圀 第　５　図

Claims (1)

    【実用新案登録請求の範囲】
  1. 配線パターン上に絶縁層パターンを重ねて配線パターン
    上の一部にフェースダウン接続用チップ接続部を形成す
    るセラミック基板において、チップ接続部となる配線パ
    ターンをセラミック基板の周辺に対し傾斜させて形成し
    、該傾斜部分の配線パターンと直角方向に絶縁層パター
    ンを形成することによって、チップ接続部を構成するこ
    とを特徴とするセラミック配線基板。
JP1983040603U 1983-03-23 1983-03-23 セラミツク配線基板 Pending JPS59146967U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983040603U JPS59146967U (ja) 1983-03-23 1983-03-23 セラミツク配線基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983040603U JPS59146967U (ja) 1983-03-23 1983-03-23 セラミツク配線基板

Publications (1)

Publication Number Publication Date
JPS59146967U true JPS59146967U (ja) 1984-10-01

Family

ID=30171219

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983040603U Pending JPS59146967U (ja) 1983-03-23 1983-03-23 セラミツク配線基板

Country Status (1)

Country Link
JP (1) JPS59146967U (ja)

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