JPS5896327A - インタ−フエイス回路 - Google Patents

インタ−フエイス回路

Info

Publication number
JPS5896327A
JPS5896327A JP19540581A JP19540581A JPS5896327A JP S5896327 A JPS5896327 A JP S5896327A JP 19540581 A JP19540581 A JP 19540581A JP 19540581 A JP19540581 A JP 19540581A JP S5896327 A JPS5896327 A JP S5896327A
Authority
JP
Japan
Prior art keywords
signal
data
gate
register
interface circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19540581A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0210978B2 (enrdf_load_html_response
Inventor
Takashi Ito
俊 伊藤
Takeshi Onishi
健 大西
Masayuki Ishida
雅之 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP19540581A priority Critical patent/JPS5896327A/ja
Publication of JPS5896327A publication Critical patent/JPS5896327A/ja
Publication of JPH0210978B2 publication Critical patent/JPH0210978B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
JP19540581A 1981-12-03 1981-12-03 インタ−フエイス回路 Granted JPS5896327A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19540581A JPS5896327A (ja) 1981-12-03 1981-12-03 インタ−フエイス回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19540581A JPS5896327A (ja) 1981-12-03 1981-12-03 インタ−フエイス回路

Publications (2)

Publication Number Publication Date
JPS5896327A true JPS5896327A (ja) 1983-06-08
JPH0210978B2 JPH0210978B2 (enrdf_load_html_response) 1990-03-12

Family

ID=16340559

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19540581A Granted JPS5896327A (ja) 1981-12-03 1981-12-03 インタ−フエイス回路

Country Status (1)

Country Link
JP (1) JPS5896327A (enrdf_load_html_response)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0381783U (enrdf_load_html_response) * 1989-12-12 1991-08-21

Also Published As

Publication number Publication date
JPH0210978B2 (enrdf_load_html_response) 1990-03-12

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