JPS589608B2 - スレツシヨ−ルドスイツチ用回路配置 - Google Patents

スレツシヨ−ルドスイツチ用回路配置

Info

Publication number
JPS589608B2
JPS589608B2 JP53133840A JP13384078A JPS589608B2 JP S589608 B2 JPS589608 B2 JP S589608B2 JP 53133840 A JP53133840 A JP 53133840A JP 13384078 A JP13384078 A JP 13384078A JP S589608 B2 JPS589608 B2 JP S589608B2
Authority
JP
Japan
Prior art keywords
collector
transistor
circuit arrangement
current mirror
amplification transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53133840A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5472946A (en
Inventor
ウオルター・アインフエルト
ゲルハルト・ユルゲン・ボツケルマン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of JPS5472946A publication Critical patent/JPS5472946A/ja
Publication of JPS589608B2 publication Critical patent/JPS589608B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H03K19/01818—Interface arrangements for integrated injection logic (I2L)
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Manipulation Of Pulses (AREA)
  • Amplifiers (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
JP53133840A 1977-11-02 1978-11-01 スレツシヨ−ルドスイツチ用回路配置 Expired JPS589608B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19772748967 DE2748967C2 (de) 1977-11-02 1977-11-02 Schaltungsanordnung für einen monolithisch integrierten Schwellwertschalter

Publications (2)

Publication Number Publication Date
JPS5472946A JPS5472946A (en) 1979-06-11
JPS589608B2 true JPS589608B2 (ja) 1983-02-22

Family

ID=6022812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53133840A Expired JPS589608B2 (ja) 1977-11-02 1978-11-01 スレツシヨ−ルドスイツチ用回路配置

Country Status (5)

Country Link
JP (1) JPS589608B2 (enrdf_load_stackoverflow)
CA (1) CA1128149A (enrdf_load_stackoverflow)
DE (1) DE2748967C2 (enrdf_load_stackoverflow)
FR (1) FR2408244A1 (enrdf_load_stackoverflow)
GB (1) GB2007452B (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2931901C2 (de) * 1979-08-07 1987-03-19 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Monolithisch integrierter Schwellwertschalter
JPS56120206A (en) * 1980-02-27 1981-09-21 Nec Corp Transistor circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2309084A1 (fr) * 1975-04-22 1976-11-19 Radiotechnique Compelec Dispositif a seuils pour circuits logiques integres

Also Published As

Publication number Publication date
FR2408244A1 (fr) 1979-06-01
DE2748967B1 (de) 1979-01-25
GB2007452A (en) 1979-05-16
FR2408244B1 (enrdf_load_stackoverflow) 1983-10-07
DE2748967C2 (de) 1983-01-13
CA1128149A (en) 1982-07-20
JPS5472946A (en) 1979-06-11
GB2007452B (en) 1982-04-15

Similar Documents

Publication Publication Date Title
JPH02179120A (ja) 負荷制御エミッタ結合論理過渡ドライバ
US4063185A (en) Direct coupling type power amplifier circuit
JPH07235868A (ja) 電流バッファ回路
EP0046498B1 (en) Bootstrapped driver circuit
JPS589608B2 (ja) スレツシヨ−ルドスイツチ用回路配置
JPS60817B2 (ja) 相補型エミツタ・フオロワ回路
US4506176A (en) Comparator circuit
EP0147635A2 (en) Gate having reduced miller capacitance
JPH03227119A (ja) Ｅｃｌ論理回路
US3443127A (en) Buffered emitter-coupled trigger circuit
US4426626A (en) Signal switching circuit
JP7116590B2 (ja) 出力回路
JP3316039B2 (ja) スイッチング回路
JPH09298870A (ja) ゲート駆動装置およびパワーモジュール
JP2891386B2 (ja) ドライバ回路
JPH042007B2 (enrdf_load_stackoverflow)
SU790331A1 (ru) Транзисторно-транзисторный логический элемент "и-или-не
JP2797621B2 (ja) コンパレータ回路
JPS6034849B2 (ja) ミユ−テイング回路
JPH0786895A (ja) 出力回路
JPH0537350A (ja) Ｅｃｌ回路
JPH0548645B2 (enrdf_load_stackoverflow)
JPH06112790A (ja) 電流制限機能付き半導体素子
JPH01245609A (ja) パルス電流出力回路
JPH0583117A (ja) Ｅｃｌ型半導体集積回路装置