JPS5833716B2 - Shotsutoki - Hekigata Denkai Kouka Transistor No. Seizouhouhou - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a Schottky barrier field effect transistor (
The present invention relates to a method for manufacturing a 5BFET (hereinafter abbreviated as 5BFET), and provides a 5BFET with particularly improved high frequency characteristics.

As shown in FIG. 1, the typical structure of a conventional 5BFET consists of forming a single crystal layer 2 with relatively low concentration of N-type conductivity on a semi-insulating gallium arsenide GaAs substrate 1, and High concentration source and drain regions 3 and 4 of the same conductivity type are formed in layer 2 at a predetermined distance apart, and source electrode 5 and drain electrode 6 are formed on these north and drain regions 3 and 4, respectively, and a single crystal layer is formed. A gate electrode 7 is formed in contact with the gate electrode 2 to form a Schottky barrier.

By applying a negative voltage to the gate electrode 7, a depletion layer is formed in the single crystal layer 2 below the gate electrode 7, thereby controlling the channel capacitance between the source and drain.

In such a 5BFET, its high frequency characteristics can be improved by either increasing the transconductance, increasing the cutoff frequency, or decreasing the series resistance.

The mutual conductance and cutoff frequency depend on the channel length, and the series resistance depends on the contact resistance of the source and drain electrodes and the spacing between the source and drain electrodes.

Gallium arsenide GaAs with Schottky barrier at gate
Although the 5BFET can operate as a super high frequency transistor, even better high frequency characteristics are desired in this case.

In order to improve such characteristics, it is necessary to further reduce the channel length L1 and the distance between the source and drain, but in the conventional 5BFET, the processing accuracy of the structure, the processing accuracy of the photoresist, and the mask alignment are Dimensional accuracy limits the reduction of channel length and source/drain spacing.

That is, to form each electrode including the gate electrode 7, a selective chipping method of electrode metal is used, and a selective diffusion method is used to form the source and drain regions 3 and 4, but these methods It is also limited by photoresist processing accuracy and mask alignment dimensional accuracy.

For example, the photoresist processing accuracy and mask alignment dimensional accuracy are such that the tilt is about 2μ, so the channel length,
Source-gate distance W, or gate-drain distance W2
, more than 2 μT (it is difficult to rub).

The present invention solves the above-mentioned problems, reduces the north gate spacing W and the gate-drain spacing W2, and at the same time makes it easy to control them, and furthermore, the manufacturing process is simple.
A method for manufacturing a BFET is provided.

FIG. 2 shows an example of a 5BFET made according to the present invention according to 1, in which 1 is a semi-insulating GaAs substrate and 2 is a relatively low concentration, e.g.
-a, a channel region is formed of an N-type GaAs single crystal layer with a thickness of 0.3μ.

3 and 4 are north and drain regions made of an N-type high concentration GaAs single crystal layer located a certain distance apart from each other on the single crystal layer 2; 5 and 6 are source and drain electrodes; 8 and 9 are respectively The north extension region, the drain extension region, and 7 are Schottky barrier type gate electrodes.

In such a structure, the distances between the gate electrode 7, the source region 3, and the drain region 4 are substantially the distances between the gate electrode 7, the source extension region 8, and the drain extension region 9; The formation of the 8-drain extension region 9 is controlled by the mask used when performing selective ion implantation, for example, by the thickness of the oxide film.

Next, an embodiment of the present invention will be explained in the order of steps with reference to FIG.

(1) An N-type GaAs single crystal layer 2 is formed on a semi-insulating GaAs substrate 1.

This single crystal layer 2 has a concentration of 5 to 10 x 1016 CrrL
−3 thickness Q, 3 tt, formed by e.g. fly taxial growth technique.

Thereafter, a C, V, D method (Chemical
An oxide film 10 of silicon dioxide S + 02 or silicon nitride Si3N4 is formed by a chemical vapor deposition method or the like.

(II) The oxide film 10 on the surface of the single crystal layer 2, which will become the source and drain regions, is removed and selective diffusion is performed through this window to form the source and drain regions 3 and 4.

(B) After removing the oxide film 10, a new oxide film is formed, and a window for the gate electrode is opened approximately in the middle of the source and drain regions 3 and 4.

Subsequently, a gate electrode metal is deposited over the entire surface of the oxide film, and photoetching is used to leave only the metal at the gate electrode 7 portion and remove the rest.

As the metal for the gate electrode 7, molybdenum, tungsten, etc., which can form a Schottky barrier even at high temperatures (up to about 600° C.), can be used.

(rV) Gate electrode 7, 'north, drain region 3
.

The thickness of this oxide film 10 is controlled to a predetermined value, for example, 0.3μ.

(V) Acid (Ions, such as sulfur ions, which penetrate into the single crystal layer 2 and form an N-type layer from the surface of the arsenic film 10' are implanted.

The ion implantation conditions at this time are that the ions are
The acceleration is selected such that ions completely pass through 0' and ions do not pass through the gate electrode 7 portion.

Specifically, the acceleration voltage is about 700 KeV.

The implantation amount is set so that the carrier concentration is more than -digit higher than that of the channel layer.
That's about it.

When this ion implantation is performed, ions do not pass through the 7 gate electrodes and the thick part of the oxide film 10' from both ends of the gate electrode 7, so ions are not implanted into the semiconductor surface, and the other semiconductor surfaces ion is implanted into.

At both ends of the gate electrode 7, the oxide film 10' has a thickness equal to the thickness of the gate electrode 7 plus the thickness of the oxide film 10' from the semiconductor surface.

Further, the width of this film thickness corresponds to the distance of the thick part of the oxide film 10' from both ends of the gate electrode.

Next, a heat treatment is performed to activate the ion implantation region within the semiconductor.

This activated region becomes a source extension region 8 and a drain extension region 9.

The heat treatment conditions for activation are a temperature at which the Schottky barrier junction of the gate electrode 7 does not collapse, specifically about 6
It is carried out at a temperature below 00°C.

(VII Source and drain regions 3 of oxide film 10',
After opening a hole in the upper part of 4 and depositing a metal such as a gold-germanium alloy on the entire surface, which will become the source and drain electrodes, photoetching is performed leaving the parts that will become the source and drain electrodes, and alloying treatment is performed. Source, drain electrode 5
, 6 are formed.

Thereafter, a window is opened in a part of the gate electrode 7, and an electrode lead wire 11 is bonded thereto.

As explained above, the method for manufacturing the 5BFET of the present invention extends the 'north and drain regions by implanting ions using the gate electrode and the oxide film formed on the side surfaces of the gate electrode as a mask. Interval W
, and the gate-drain distance W2 are determined by the thickness of the oxide film, which is easy to control, and their values can be set more accurately than in the past.

Furthermore, when forming a gate electrode between a source region and a drain region, there is no need to align the gate electrode with a mask, and even if the gate electrode is placed at any position between both regions, the source extension region and drain extension region can be formed. When selective ion implantation is performed, the ions are selectively implanted into the semiconductor excluding only the thickness valve of the oxide film under the gate electrode and at both ends of the gate electrode. An extension area is placed.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional 5BFET, FIG. 2 is a sectional view of a 5BFET according to an embodiment of the present invention, and FIG. 3 is a sectional view showing the same embodiment in the order of manufacturing steps. DESCRIPTION OF SYMBOLS 1... GaAs base, 2... Single crystal layer, 3... Source region, 4... Drain region, 5... Panose electrode, 6...-Drain electrode, 7...Gate electrode, 8...
Source extension region, 9...Drain extension region.

Claims (1)

[Claims] 1 Semiconductor substrate (this is a step of forming a semiconductor single crystal layer of the conductivity type, a step of forming source and drain regions consisting of high concentration regions of the same conductivity type at a predetermined distance from each other in the single crystal layer I, a step of forming a semiconductor substrate of the same conductivity type, and a step of forming a semiconductor single crystal layer of the same conductivity type, a step of forming a semiconductor substrate of the same conductivity type, forming a Schottky barrier type gate electrode on the surface of the single crystal layer; depositing an oxide film covering the gate electrode, the source and drain regions, and each surface of the single crystal layer; Using the oxide film formed on the side surface of the gate electrode as a mask, ions of the same conductivity type as the single crystal layer are implanted to a certain depth to form a north extension region and a drain extension region extending from each source and drain region to the gate electrode side. A method for manufacturing a Schottky barrier field effect transistor, comprising the steps of: removing the oxide film and forming a source electrode and a drain electrode in the source and drain regions, respectively.