JPS5856470A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5856470A JPS5856470A JP15524181A JP15524181A JPS5856470A JP S5856470 A JPS5856470 A JP S5856470A JP 15524181 A JP15524181 A JP 15524181A JP 15524181 A JP15524181 A JP 15524181A JP S5856470 A JPS5856470 A JP S5856470A
- Authority
- JP
- Japan
- Prior art keywords
- forming
- layer
- substrate
- film
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000012535 impurity Substances 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 12
- 230000001681 protective effect Effects 0.000 claims abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 54
- 239000000377 silicon dioxide Substances 0.000 claims description 26
- 235000012239 silicon dioxide Nutrition 0.000 claims description 25
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 17
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 239000003870 refractory metal Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims 4
- 238000005034 decoration Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 230000005669 field effect Effects 0.000 abstract description 6
- 230000004888 barrier function Effects 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 46
- 239000010931 gold Substances 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 108091006146 Channels Proteins 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 101100366935 Caenorhabditis elegans sto-2 gene Proteins 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- 235000011511 Diospyros Nutrition 0.000 description 1
- 241000723267 Diospyros Species 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 229910001096 P alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- VQHSOMBJVWLPSR-UHFFFAOYSA-N lactitol Chemical compound OCC(O)C(O)C(C(O)CO)OC1OC(CO)C(O)C(O)C1O VQHSOMBJVWLPSR-UHFFFAOYSA-N 0.000 description 1
- 235000010448 lactitol Nutrition 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関する。特に、牛絶縁
性砒化ガリュウム（ＧａＡ８）を基板と−し、この基板
表層にイオン注入されたｎ型不純物層をチャンネルとし
、このチャンネル領域上に形成されたりフラクトリーメ
タルよシなるゲート電極を有する半導体装置の製造方法
の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device. In particular, the substrate is made of insulating gallium arsenide (GaA8), the channel is an n-type impurity layer ion-implanted into the surface layer of the substrate, and the gate electrode is formed on the channel region or made of a factory metal. This invention relates to improvements in methods for manufacturing semiconductor devices.
砒化ガリ具つム（ＧａＡａ）はこれにクローム（Ｏｒ
）等をドープすると半絶縁性となるため、上記の如くこ
の基板表層に十分大量のｎ型不純物を導入してｎ型チャ
ンネルを形成し、このチャンネル上にショットキバリヤ
型ゲートを形成し電界効果トランジスタを製造すること
が多い。砒化ガリエウム（Ｇａ Ａｓ ’）中において
は電子移動度が速いため、動作速度の速い半導体装置を
製造することがｆきる利点がある他、微細パターンの形
成も比較的容易なため、高周波用としても有利〒ある。Arsenide galitsumu (GaAa) is added to this with chromium (Or
) etc., it becomes semi-insulating. Therefore, as mentioned above, a sufficiently large amount of n-type impurity is introduced into the surface layer of this substrate to form an n-type channel, and a Schottky barrier gate is formed on this channel to form a field effect transistor. is often manufactured. Since electron mobility is high in gallium arsenide (GaAs'), it has the advantage of being able to manufacture semiconductor devices with high operating speeds, and it is also relatively easy to form fine patterns, making it suitable for high frequency applications. There is an advantage.
ソース・ドレイン電極は金／金・ゲルマニエウム（Ａｕ
／Ａｕ−（）ｅ）ヲ使用する場合が多い。ダート電極と
しては歴史的にはアルミニニウム（Ａ／）を使用した時
代もあったが、特にノーマリオフ型（エンハンスメント
型）となすためにはゲートとソース・ドレイン間のデプ
リション領域をなくしたいという要望があるため、ゲー
トをマスクとしてｎ型不純物をイオン注入して、ダート
に対してセルファラインドｎ型ソース・ドレイン領域の
形成を可能とするため、ゲート材料はチタン（Ｔｉ）、
タングステン（Ｗ）等のりフラクトリーメタル或いはそ
れらのシリサイ２合金に移行した。具体的には、第１図
に示すように、半絶縁性砒化ガリュウム（ｏａＡｓ）基
板ｌの素子形成領域にｎ型不純物をイオン注入してｎ型
層２を形成した後、チタン（Ｔｉ）、タングステン（Ｗ
）等のりフラクトリーメタルよりなるシ璽ットキノリャ
ゲート３を形成した後、素子形成領域以外の領域を７オ
トレジスト膜４〒覆い再びｎ型不純物をイオン注入して
ｎ＋１１層よりなるソース領域５とドレイン領域６とを
形成する。The source/drain electrodes are gold/gold/germanium (Au).
/Au-()e) is often used. Historically, there was a time when aluminum (A/) was used as the dirt electrode, but there was a desire to eliminate the depletion region between the gate and source/drain, especially in order to create a normally-off type (enhancement type). Therefore, the gate material is titanium (Ti), in order to form a self-aligned n-type source/drain region for dirt by ion-implanting n-type impurities using the gate as a mask.
There has been a transition to glue factory metals such as tungsten (W) or their Silice 2 alloys. Specifically, as shown in FIG. 1, an n-type impurity is ion-implanted into the element formation region of a semi-insulating gallium arsenide (OAAs) substrate l to form an n-type layer 2, and then titanium (Ti), Tungsten (W
), etc. After forming the sheet metal gate 3 made of a factory metal, the area other than the element forming area is covered with a photoresist film 4, and n-type impurities are ion-implanted again to form a source region 5 made of an n+11 layer. A drain region 6 is formed.
ところが、ソース領域５とドレイン領域６とが熱処理工
程期間中に第２図に示すようにゲート電′！＃３の下部
迄拡散する傾向があシ、ゲート電極３の両端下部領域の
不純物濃度が極めて高濃度となるため、ゲートの逆方向
絶縁耐力の低下を惹起する欠点がある。更に、ゲート電
極３のエラｆ”グ工程において、ゲート電極３が第３図
に示すように台形となる傾向があり、この場合はグー、
ト端部な貫通してｎ型不純物がイオン注入されるため、
上記のゲート電極３の両端下部領域の不純物濃度が高く
なる傾向は更に強められ、ダートの逆方向絶縁耐力の低
下を惹起する欠点は更に顕著なものとなる。However, as shown in FIG. 2, the source region 5 and drain region 6 are exposed to the gate voltage during the heat treatment process. There is a tendency for the impurity to diffuse to the bottom of #3, and the impurity concentration in the lower regions at both ends of the gate electrode 3 becomes extremely high, which has the disadvantage of causing a decrease in the reverse dielectric strength of the gate. Furthermore, in the process of erecting the gate electrode 3, the gate electrode 3 tends to become trapezoidal as shown in FIG.
Since n-type impurity ions are implanted through the top end,
The above-mentioned tendency for the impurity concentration in the regions below both ends of the gate electrode 3 to become high is further strengthened, and the drawback of causing a decrease in the reverse dielectric strength of the dirt becomes even more remarkable.
本発明の目的はこの欠点を解消することにア抄、半絶縁
性砒化ガリュウム（ＧａＡｅ）を基板とし、この基板表
層の素子形成領域にｎ型不純物をイオン注入の上熱処理
して活性層すなわちチャンネルを形成し、このチャンネ
ル領域上のゲート電極形成領域上にり７ラクトリーメタ
ルよねなるゲート電体を形成し、仁のゲート電極をマス
クとして再びｎ型不純物をイオン注入してソース・ドレ
インを形成し、フィールＰ上及びダート電極上を絶縁す
る目的をもって基板全面に絶縁物層を形成し、ソース・
ドレイン上に電極窓明けをなして、ここにソース・ドレ
イン電極・配線を配設してなる電界効果トランジスタに
おいて、ゲート電極とソース・ドレイン領域との間の逆
方向絶縁耐力の向上した電界効果トランジスタを製造す
る方法を提供することにある。The purpose of the present invention is to eliminate this drawback by using semi-insulating gallium arsenide (GaAe) as a substrate, implanting n-type impurities into the element formation region on the surface layer of the substrate, and heat-treating the active layer, that is, the channel. A gate electrode is formed on the gate electrode formation region on the channel region, and a gate electric body made of 7 lacty metal is formed, and an n-type impurity is ion-implanted again using the second gate electrode as a mask to form the source and drain. Then, an insulating layer is formed on the entire surface of the substrate for the purpose of insulating the top of the field P and the top of the dirt electrode, and the source
A field effect transistor with improved reverse dielectric strength between a gate electrode and a source/drain region, in which an electrode window is formed above the drain and source/drain electrodes/wirings are disposed therein. The purpose is to provide a method for manufacturing.
その要旨性、リフラクトリ−メタルよりなるゲート電極
をマスクとしてｎ型不純物をイオン注入してソース・ド
レインを形成するに際し、マスクとして機能するゲート
電極の側面に注入イオンに対するノ号リヤを設け、この
ノ９リヤによってゲート電極直近の活性層中にはイオン
注入がなされず、ゲート電極直近の活性層中のｎ型不純
物濃度゛は過度に上昇しないようにすることにあり、そ
の／？リヤの材料及び形成方法の相違により決定される
二つの独立した発明を包含する。まず、第１の発明はそ
の／々リヤの材料を二酸化シリコン（８１０２）のよう
な絶縁物とし、ゲート電極形成後、基板全面ニ薄＜ ５
００〜１，０００ Ｘ 程１１’ニ二酸化Ｖ ！ｊ ：
ｙ ン（８１０１）層を形成し、更にイオン注入マスク
用の７オトレ・クスト膜を厚く１〜２μｍ程度形成した
後、このフォトレジスト膜を素子形成領域上から除去し
、その除去ノンヘゲート電極部をマスクとしてｎｆｉ不
純物をイオン注入した後使用済みの７オトレジスト膜を
除去して、熱処理を施してソース・ドレインのｎ＋Ｍを
形成し、ソース・ドレイン領域上の二酸化シリコン（８
１０，）層にソース・ドレイン電極用窓明けをなしてこ
こにソース・ｒしく ｙ電極とこれに接続される配線を
なすことにある０このとき、基板全面に薄く形成された
二酸化シリコン（ＳｔＯ２）層が、ゲート電極側面にお
いてはダート電極の高さに相当する厚さとなるの！、イ
オン注入に対しノ々リヤとしての機能を十分発揮すると
ともに、熱処理に対しては保護膜としての機能な発揮す
る。なお、本発明にあっては、上記のイオン注入に対す
るマスクとして使用された二酸化シリコン（Ｓ１０□）
層は損傷を受けていることが一般１ある故、一旦すべて
これを除去し、あらためて別の二酸化シリコン（Ｓ１Ｏ
２）層を形成して、これをゲート上の絶縁層とフィール
Ｐ絶縁層として使用することはより有効である。次に、
第２の発明はその／々リヤの材料をフォトレジストとし
、ゲート電極形成後、基板全面に比較的厚＜ ５，００
０〜６，０００Ｘ穆聞に二酸化シリコン（８１０，）層
を形成した後これを素子形成領域上から除去して素子形
成領域を露出させた後、基板全面にフォトレジスト膜を
α２μｍ程度の厚さに塗布する。その後、ｎ型不純物を
イオン注入し、使用済みのフォトレジスト膜を除去して
二酸化シリコン（８１０ｇ）、窒化シリコン（ｓｔ３ｎ
４）等の保護膜を形成して熱処理を施し、ソース・ドレ
インのｎ＋＃を形成し、この保護膜として使用された二
酸化シリコン（８１０２）、窒化シリコン（Ｓｉ３Ｎ４
）等の膜をそのｔまゲート上の絶縁層とフィールＰ絶縁
層として使用することとし、コレにソース・ドレイン電
極用窓明けをなしてここにソース・ドレイン電極とこれ
に接続される配線をなすことにある。このとき、第１の
発明の場合と同様、基板全面に塗布されたフォトレジス
ト膜がゲート電極側面においてはゲート電極の高さに相
当する厚さとなるので、イオン注入に対しノ９リヤとし
ての機柿な十分発揮することとなる。この第２の発明の
第１の発明に対する利点はイオン注入に対するバリヤ層
の形成が容易であり、かつ、イオン注入に要するエネル
ギーも少なく制御も容易′１％あること〒ある０なお、
この発明においても、素子形成領域を除く慴域に形成し
た比較的厚い二酸化シリコン（ｓｉｏ２）層を一旦除去
して、あらためて、別の二酸化シリコン（ｓｉｏ２）Ｍ
ｉを形成して、これをゲート上の絶Ｒ層とフィールＰ絶
縁層として使用することは、段差の解消ひいては断線め
防止という点からも有効″Ｔ！ある。Its gist is that when forming sources and drains by ion-implanting n-type impurities using a gate electrode made of refractory metal as a mask, a groove for the implanted ions is provided on the side surface of the gate electrode, which functions as a mask. The goal is to prevent ion implantation into the active layer in the vicinity of the gate electrode and to prevent the n-type impurity concentration in the active layer in the vicinity of the gate electrode from increasing excessively. It encompasses two independent inventions determined by the difference in material and method of forming the rear. First, the first invention uses an insulator such as silicon dioxide (8102) as the material for the rear layer, and after forming the gate electrode, the entire surface of the substrate is thinner than 5.
00~1,000 X about 11' dioxidation V! j:
After forming a y-on (8101) layer and further forming a 7-Otre-Cust film for an ion implantation mask with a thickness of about 1 to 2 μm, this photoresist film is removed from above the element formation area, and the removed non-hegate electrode portion is removed. After ion-implanting NFI impurities as a mask, the used 7 photoresist film is removed, heat treatment is performed to form source/drain n+M, and silicon dioxide (8
10) The purpose is to open windows for the source/drain electrodes in the layer to form the source/r y electrodes and the wiring connected to them. At this time, silicon dioxide (StO2 ) layer has a thickness equivalent to the height of the dirt electrode on the side of the gate electrode! It fully functions as a protective film for ion implantation, and also functions as a protective film for heat treatment. In addition, in the present invention, silicon dioxide (S10□) used as a mask for the above ion implantation
Since the layer is generally damaged1, it is removed completely and replaced with another layer of silicon dioxide (S1O).
2) It is more effective to form a layer and use it as an insulating layer on the gate and as a field P insulating layer. next,
The second invention uses a photoresist as the material for the rear layer, and after forming the gate electrode, a relatively thick layer of <5,000 mm is applied to the entire surface of the substrate.
After forming a silicon dioxide (810,) layer with a thickness of 0 to 6,000X, removing this layer from above the element formation area to expose the element formation area, a photoresist film with a thickness of about 2 μm is applied over the entire surface of the substrate. Apply to. After that, n-type impurities were ion-implanted, the used photoresist film was removed, and silicon dioxide (810g) and silicon nitride (st3n) were added.
A protective film such as 4) was formed and heat treated to form the source/drain n+#, and the silicon dioxide (8102) and silicon nitride (Si3N4
) etc. will be used as the insulating layer on the gate and the field P insulating layer, and a window for the source/drain electrode will be made in this, and the source/drain electrode and the wiring connected to it will be placed here. It's in what you do. At this time, as in the case of the first invention, the photoresist film coated on the entire surface of the substrate has a thickness corresponding to the height of the gate electrode on the side surface of the gate electrode, so it is difficult to prevent ion implantation from occurring. The persimmons will show their full potential. The advantage of this second invention over the first invention is that it is easy to form a barrier layer against ion implantation, and the energy required for ion implantation is low and control is easy.
In this invention as well, the relatively thick silicon dioxide (SIO2) layer formed in the area excluding the element formation region is removed, and then another silicon dioxide (SIO2) layer is added.
It is effective to form a layer i and use it as an insulating layer on the gate and as an insulating layer on the field P, from the viewpoint of eliminating the step difference and also preventing disconnection.
以下図面を参照しつつ、本出願の第１の発明に係る一実
施例について、その主要各工程を説明し、本発明の構成
と特有の効果とを明らかにする。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The main steps of an embodiment according to the first invention of the present application will be explained below with reference to the drawings, and the structure and unique effects of the present invention will be clarified.
第４図参照
クローム（Ｏｒ）等のＰ−プされた牛絶縁性砒化ガリエ
ウム（ＧａＡｓ）基板１の素子形成領域にマスク等を使
用して選択的にシリコン（８１）等のｎ型不純物をイオ
ン注入した後、基板１上に二酸化シリ：ｌ ｙ （ｓｉ
ｏ、） 、窒化シリ：ｆ ７ （８１３Ｎ、）等の保護
膜（図示せず）を形成の上熱処理してｎ型層２を形成す
る。次に、保護膜（図示せず）を除去した後、蒸着、ス
パッタ等の方法を使用して、チタン（Ｔｉ）、タングス
テン（Ｗ）等のりフラクトリーメタル或いはそのシリサ
イド合金よりなる＃（図示せず）を全面に形成し、フォ
トリソグラフィー法を使用してこの金属またはシリサイ
ドよりなる層の大部分をゲート領域上以外から除去し、
ショットキノ９リヤゲート３を形成する。Refer to Fig. 4. Using a mask or the like, selectively ionize n-type impurities such as silicon (81) into the element formation region of a P-plated insulating gallium arsenide (GaAs) substrate 1 such as chromium (Or). After implantation, silicon dioxide: ly (si
After forming a protective film (not shown) such as silicon nitride: f 7 (813N, ) and heat-treating, the n-type layer 2 is formed. Next, after removing the protective film (not shown), using a method such as vapor deposition or sputtering, a # (not shown) made of a glue factory metal such as titanium (Ti) or tungsten (W) or a silicide alloy thereof is deposited. ) is formed on the entire surface, and most of the metal or silicide layer is removed from areas other than the gate area using photolithography.
Form Schottkino 9 rear gate 3.
第５図参照
表面一部にゲート電極３を有する基板ｌの全面に二酸化
シリコン（Ｓｉｎ２）層８をうす（，５００〜１．０Ｏ
ＯＸ程変に形成する。この形成方法は化学的気相成長法
が適当である。つづいて、基板全面にフォトレジスト膜
９を比較的厚く１〜２μｍ程度の厚さに形成した後フォ
トリソグラフィー法を使用して素子形成領域上から除去
する。Refer to FIG. 5. A thin silicon dioxide (Sin2) layer 8 is formed on the entire surface of the substrate l having a gate electrode 3 on a part of the surface (500~1.0O
OX forms strangely. A chemical vapor deposition method is suitable for this formation method. Subsequently, a photoresist film 9 is formed on the entire surface of the substrate to a relatively thick thickness of about 1 to 2 .mu.m, and then removed from the element formation region using photolithography.
第６図参照
前工程でノぐターニングされたフォトレジスト膜９をマ
スクとして、シリコン（Ｓｌ）等のｎ 型不１４物をイ
オン注入する０レジスト除去につづいて、熱処理を施し
て、ｎ＋層であるノース１Ｏ１Ｐレイン１１を形成する
。このとき、ゲート電極３の側面に堆積した二酸化シリ
コン（ＥｌｉＯ，）層８が注入イオンに対するバリヤと
して機能し、ソースｌＯ、ドレイン１１とゲート電極３
との端部は相互に接触することはなく、５０ＯＡ相度の
間隔が残留するから、ゲート電極３の下部領域のｎ型不
純物濃度が過度に大きくなることはない０又、熱処理に
あたって、二酸化シリコン（Ｓ１０□）層８は保護膜と
して機能する０
第７図参照
ソース１０、ｒレインｌｌ上と所望によりゲート電極３
上の領域において、二酸化シリコン（ｓｔｏ２）膜８に
開口を設ける。この３０の形成方法は、フォトリソグラ
フィー法を使用することが容易フある。蒸着法またはス
・ぞツタ法により金／金・ゲルマニュウム（Ａｕ ／
Ａｕ −Ｇｅ ）層を基板全面に形成し、所望のパター
ニングをなして、ソース電極・配線１２、ドレイン電極
・配線１３、ゲート配線１４を完成する０
以上説明せるとおり、本発明によれば、半絶縁性砒化ガ
リエウム（ＧａＡｓ）を基板とし、この基板表層の素子
形成領域にｎ型活性層を形成し、この活性層上にリフラ
クトリ−メタルまたはそのシリサイＰ合金よりなるゲー
ト電極を形成し、このゲート電極をマスクとしてｎ型不
純物をイオン注入してｎ１域よりなるソース・ドレイン
を形成する電界効果トランジスタの製造方法において、
マスクとして機能するゲート電極の側面に二酸化シリコ
ン（Ｓ１Ｏ，）よりなるノ９リヤが設けらｈているため
、ゲート峨称とソース・ドレイン領域との間には、ｎ型
不純物濃度が過大フある領域が存在せず、ゲート電極と
ソース・ドレイン領域との間の逆方向Ｐ縁耐力の向上し
り電界効果トランジスタを提供することができる。Referring to FIG. 6, using the photoresist film 9 which has been turned in the previous step as a mask, ions of an n-type non-conductor such as silicon (Sl) are implanted.Following the removal of the resist, heat treatment is performed to form an n+ layer. A certain north 1O1P rain 11 is formed. At this time, a silicon dioxide (EliO,) layer 8 deposited on the side surface of the gate electrode 3 functions as a barrier against the implanted ions, and the source lO, drain 11 and gate electrode 3
Since the ends of the gate electrodes do not contact each other and a gap of 50 OA remains, the n-type impurity concentration in the lower region of the gate electrode 3 does not become excessively large. (S10□) Layer 8 functions as a protective film 0 See FIG. 7 Source 10, r layer ll and optionally gate electrode 3
An opening is provided in the silicon dioxide (sto2) film 8 in the upper region. As a method for forming this layer 30, it is easy to use a photolithography method. Gold/gold/germanium (Au/
As explained above, according to the present invention, a layer of Au-Ge) is formed on the entire surface of the substrate, and the desired patterning is performed to complete the source electrode/wiring 12, the drain electrode/wiring 13, and the gate wiring 14. Using insulating gallium arsenide (GaAs) as a substrate, an n-type active layer is formed in the element formation region on the surface layer of the substrate, and a gate electrode made of refractory metal or its silica P alloy is formed on this active layer. In a method for manufacturing a field effect transistor in which a source/drain consisting of an n1 region is formed by ion-implanting n-type impurities using an electrode as a mask,
Since a layer made of silicon dioxide (S1O,) is provided on the side surface of the gate electrode that functions as a mask, there is an excessive n-type impurity concentration between the gate electrode and the source/drain region. It is possible to provide a field effect transistor in which there is no region and the reverse P edge strength between the gate electrode and the source/drain region is improved.
又、本発明とはノ々リヤの材料と製造工程とが相違する
が、同一のＲ想にもとづき、−一の目的を達成する第２
の発明のあることは上記発明の要約の項に述べたとおり
である０その主たる相違は・々リヤとして二酸化シリコ
ン（ｓｔｏｚ）層に代えてフォトレジスト膜を使用する
ことにあり、この変更にともなって製造工程は大幅に変
更されるが、基本壁念は全く同一″′ｒ！あるからこの
第２の発明に係る実施例の記載は省略する０Furthermore, although the material and manufacturing process of the Nonoriya are different from the present invention, based on the same R idea, a second method that achieves the first objective is
As stated in the summary of the invention above, the main difference lies in the use of a photoresist film instead of a silicon dioxide (STOZ) layer as the layer, and this change Although the manufacturing process is significantly changed, the basic idea is exactly the same. Therefore, the description of the embodiment according to the second invention will be omitted.
第１図は砒化ガリエウムを基板とする電界効果トランジ
スタの概念的層構造断面図であるＯ第２図、第３図は本
発明の解決しようとする欠漬を説明するための訣明図で
ある０第４乃至第７図は本出願に係る第１の発明の一実
施例にかかる半導体装置の製造方法の主要各工程完了後
の基板断面図−Ｉ！Ｉある。
１・・・牛絶縁性基板、２・・・ｎ型層よりなる活性層
、３・・・す７ラクトリーメタルまたはそのシリサイＰ
よりなるショットキノ々リヤゲート電極、４・・・フォ
トレジスト膜、５・・・ソース領域、６・・・ドレイン
領域、８・・・二酸化シリコン層、９・・・フォトレジ
スト膜、１０・・・ソース、１１・・・ドレイン、１２
・・・ソース電極・配線、１３・・・ドレイン電極・配
線、１４・・・ゲート配線。
第４図Figure 1 is a cross-sectional view of a conceptual layer structure of a field effect transistor using gallium arsenide as a substrate. 0 FIGS. 4 to 7 are cross-sectional views of the substrate after completion of each main process of the method for manufacturing a semiconductor device according to an embodiment of the first invention according to the present application - I! I have one. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Active layer consisting of an n-type layer, 3... 7 Lactoly metal or its silicide P
4... Photoresist film, 5... Source region, 6... Drain region, 8... Silicon dioxide layer, 9... Photoresist film, 10... Source, 11...Drain, 12
... Source electrode/wiring, 13... Drain electrode/wiring, 14... Gate wiring. Figure 4
Claims (1)
素子形成領域に選択的にｎ型不純物をイオン注入した後
前記基板表面上に熱処理用保護膜を形成して熱処理を施
して活性層を形成し、（０）前記保護膜を除去した後、
前記基板全面にり７ラクトリ一メタル層を形成して該リ
フラ、クトリーメタル層をゲート形成領埴土以外から除
去してゲート電接を形成し、（−ウ前記基板全面に絶縁
層を薄く、更に、イオン注入のマスク膜を厚く形成し、
該マスク膜を素子形成領域上から除去し、に）該マスク
膜の除去された領域へｎ型不純物をイオン注入した後熱
処理を施してソース・Ｐレインを形成し、（ホ）電極。 形成用開口を形成して、（へ）電極・配線を形成する工
程よりなる牛導体装貴の製造方法。 （２）前記イオン注入によりソース・ドレインヲ形成し
、前記マスク膜を除去した後、一旦帥記絶縁層を除去し
、新たに、別の絶縁層を形成し、紋別の絶縁層に電極形
成用開口を形成して電極・配線を形成する工程よりなる
特許請求の範囲第１項記載の２牛導体装曾の製造方法。 （３ンげ）牛Ｐ！傍性砒化ガリ瓢つムよりなる基板表面
の素子形成領域に選択的にｎ型不純物をイオン注入した
後前記基板表面上に熱処理用保護膜を形成して熱処理を
施して活性層を形成し、（ロ）前記Ｏｌ！護膜を除去し
た後、前Ｖ基板全面にリフラクトリ−メタル層を形成し
て骸リフラクトリーメタル層をゲート形成領埴土以外か
ら除去してゲートを形成し、ＰＩ前記基板表面の素子形
成領域上以外の領域に選択的にイオン注入マスク層を影
成し、に）更に前記基板全面にフォトレジスト膜を形成
し、（ホ）ｎ型不純物を該フォトレジスト膜を貫通して
イオン注入し、（へ）前記フォトレジスト膜を除去した
後、前記基板全面に二酸化シリコン膜を形成した後熱処
理を施してノース・Ｐレインを形成し、（ト）′ｄ１．
極形成円形成用開口して、（イ）電極・配線を形成する
工程よりなる牛導体装置の製造方法。 （４１７−ｘ・ｐ ｖイン形成のための前記イオン注入
終了後、前記フォトレジスト膜と前記素子形成領塚上以
外の領域に選択的に形成された二酸化シリコン層とを除
去し、新たに、別の二酸化シリコン層を形成し、該別の
二酸化シリコン層に電極形成用開口を形成して電極・配
線を形成する工程よりなる特許請求の範囲第３項記載の
半導体装置の製造方法。[Scope of Claims] (IIK) After selectively ion-implanting n-type impurities into the element formation region on the surface of the substrate, which is made of an insulating arsenide film, a protective film for heat treatment is formed on the surface of the substrate. After performing heat treatment to form an active layer, (0) removing the protective film,
A seven-layer metal layer is formed on the entire surface of the substrate, and the refractory metal layer is removed from areas other than the gate formation area to form a gate electrical contact. , forming a thick mask film for ion implantation,
The mask film is removed from above the element formation region, (b) n-type impurities are ion-implanted into the region from which the mask film has been removed, and then a heat treatment is performed to form a source/P-rain, and (e) an electrode is formed. A manufacturing method for a cow conductor decoration, which comprises the steps of forming a forming opening and (to) forming an electrode/wiring. (2) After forming the source and drain by the ion implantation and removing the mask film, the first insulating layer is removed, another insulating layer is newly formed, and an opening for electrode formation is formed in the separate insulating layer. 2. A method for manufacturing a double conductor assembly according to claim 1, which comprises a step of forming electrodes and wiring by forming a conductor. (3) Cow P! After selectively ion-implanting n-type impurities into an element formation region on the surface of a substrate made of parasonic gallium arsenide, forming a protective film for heat treatment on the surface of the substrate and performing heat treatment to form an active layer; (b) Said Ol! After removing the protective film, a refractory metal layer is formed on the entire surface of the front V substrate, and the refractory metal layer is removed from areas other than the gate formation area to form a gate, and the PI is formed on the surface of the PI substrate other than the element formation area. (b) further forming a photoresist film over the entire surface of the substrate; (v) ion-implanting n-type impurities through the photoresist film; ) After removing the photoresist film, a silicon dioxide film is formed on the entire surface of the substrate, and then a heat treatment is performed to form a north P-rain, (g)'d1.
A method for manufacturing a conductor device comprising the steps of: forming an opening for forming a pole-forming circle; and (a) forming an electrode/wiring. (After completing the ion implantation for forming the 417-x.pv-in, remove the photoresist film and the silicon dioxide layer selectively formed in the area other than on the element formation mound, and newly separate the 4. The method of manufacturing a semiconductor device according to claim 3, comprising the steps of: forming a silicon dioxide layer, and forming electrode formation openings in the other silicon dioxide layer to form electrodes and wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15524181A JPS5856470A (en) | 1981-09-30 | 1981-09-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15524181A JPS5856470A (en) | 1981-09-30 | 1981-09-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5856470A true JPS5856470A (en) | 1983-04-04 |
Family
ID=15601615
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15524181A Pending JPS5856470A (en) | 1981-09-30 | 1981-09-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5856470A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6086866A (en) * | 1983-10-19 | 1985-05-16 | Matsushita Electronics Corp | Manufacture of field effect transistor |
| JPS63179579A (en) * | 1987-01-20 | 1988-07-23 | Nec Corp | Manufacture of compound semiconductor device |
| US5081052A (en) * | 1986-06-25 | 1992-01-14 | Hitachi, Ltd. | ROM and process for producing the same |
| US5219777A (en) * | 1991-06-14 | 1993-06-15 | Gold Star Electron Co., Ltd. | Metal oxide semiconductor field effect transistor and method of making the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5012984A (en) * | 1973-06-01 | 1975-02-10 | ||
| JPS5267982A (en) * | 1975-12-03 | 1977-06-06 | Sanyo Electric Co Ltd | Manufacture of schottky barrier type field effect transistor |
-
1981
- 1981-09-30 JP JP15524181A patent/JPS5856470A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5012984A (en) * | 1973-06-01 | 1975-02-10 | ||
| JPS5267982A (en) * | 1975-12-03 | 1977-06-06 | Sanyo Electric Co Ltd | Manufacture of schottky barrier type field effect transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6086866A (en) * | 1983-10-19 | 1985-05-16 | Matsushita Electronics Corp | Manufacture of field effect transistor |
| US5081052A (en) * | 1986-06-25 | 1992-01-14 | Hitachi, Ltd. | ROM and process for producing the same |
| JPS63179579A (en) * | 1987-01-20 | 1988-07-23 | Nec Corp | Manufacture of compound semiconductor device |
| US5219777A (en) * | 1991-06-14 | 1993-06-15 | Gold Star Electron Co., Ltd. | Metal oxide semiconductor field effect transistor and method of making the same |
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