JPH0340438A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To contrive the stable manufacture of a field-effect transistor by a method wherein a gate length is controlled by the thickness of a second insulating film using a multiple deposition method. CONSTITUTION:A first insulating film 3 is applied on a semi-insulative GaAs substrate 2 with an N-type layer 1 formed in it by ion implantation and a window is opened in the photoresist. Then, a second insulating film 4 dissimilar to the film 3 is deposited by a multiple deposition method in such a way as to cover the opening part. The film 4 is etched by an RIE method to provide an opening part on the layer 1. A metal layer 5 formed by normal deposition of a high-melting point metal is formed, the surface of the layer 5 is flattened by a resist 6 and the layer 5 is etched using the resist 6 as a mask and is used as a gate electrode 7. The film 3 is removed by a wet etching method and an ion implantation is performed using the electrode 7 and the film 4 as masks to form n<+> layers 8 which are impurity regions. Then, the film 4 is removed by wet etching and an ion-implantation is performed using the electrode 7 as a mask to form n' layers 9, which are thinner than the layers 8 and have an impurity concentration stronger than that of the layer 1. Lastly, the whose surface is covered with an insulating film 10 and an annealing is performed to activate. By such a way, an LDD structure can stably be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a self-aligned manufacturing method of a field effect transistor (hereinafter abbreviated as FET) having a Schottky gate electrode.

(Prior art) Generally, an FE with an extremely short gate length and an LDD structure
T forms the gate portion using a self-aligned method.

A basic conventional example will be explained based on FIG.

FIG. 2 is a process sectional view showing a conventional FET manufacturing method. In the figure, nNl2 is formed on a semi-insulating GaAs substrate 11 by ion implantation, and a high melting point metal 13 such as tungsten is deposited thereon. and high melting point total bending 1
A photoresist film 14 is coated on the photoresist film 14 and exposed to light, and the photoresist film is removed leaving a portion where a gate electrode will be formed (FIG. 2(a)).

Next, the high melting point metal 13 is etched using the photoresist film 14 as a mask using the RIE method. At this time, if you make it slightly overetched, it will become a gate? The side surface of I[ is etched, and the gate 'l'! is shorter than the gate length patterned with the photoresist film 14. ! A pole 15 can be obtained (FIG. 2(b)). And photoresist film 14
After removing the insulating film 16, an insulating film 16 is applied to the entire surface, and through implantation is performed through the insulating film 16 using an ion implantation method.
An impurity region and an n0 layer 17, which will become source and drain regions, are formed (FIG. 2(C)).

After that, the insulating film 16 is removed, and ions are implanted using the gate electrode 15 as a mask to form an impurity region n'PFfJ18 having an intermediate concentration between the n layer 12 and n'')!17.
112 and the n+ layer 17 (FIG. 2(d)).

(Problems to be Solved by the Invention) The conventionally formed FET described above has the drawback that the substrate surface is damaged when the high melting point metal is excessively etched by the RIE method. This damage causes surface depletion on the surface of the n' layer, increasing source resistance, etc.
This was not preferable in terms of FET fabrication because it caused deterioration of T characteristics. Furthermore, since a gate electrode with an extremely narrow line width is formed singly, there is also the drawback that it collapses during the process.

An object of the present invention is to solve the drawbacks of the conventional FET and to form an FET with an extremely short gate length stably using an easy exposure technique such as photolithography without damaging the surface. An object of the present invention is to provide a manufacturing method.

(Means for Solving the Problems) The method for manufacturing an FET of the present invention includes the steps of forming a first film having a new type of first opening on a semiconductor conductive layer; , multiple depositing a second film on the first film, and etching the second film to form a second opening smaller than the first opening above the first opening. The first step is to form an electrode using the second opening as a mask.The first film is removed, and ions are implanted using the electrode and second film as a mask. a step of forming an impurity region; a step of removing the second film and performing ion implantation using the electrode as a mask to form a second impurity region having a higher concentration than the conductive layer and a lower concentration than the first impurity region; , which includes a step of covering the entire surface with a third film and performing annealing and activation.

(Function) With the above configuration, the present invention uses a multiple deposition method to achieve
A gate electrode with an extremely short gate length can be formed using photolithography. At this time, since the gate electrode is supported by the second film on both sides, it is prevented from falling during the process.

It is stable. Furthermore, when removing the first film and the second film, a method that causes less damage to the substrate surface, such as wet etching, can be used, so FE
It is also possible to prevent deterioration of T characteristics.

(Example) An embodiment of the present invention will be described based on FIG.

The second drawing is a cross-sectional view showing the method for manufacturing the FET of the present invention. In the same figure, a first insulating film 3 is coated on a semi-insulating GaAs substrate 2 on which an n-type conductor, which will become a channel of an FET, is formed by ion implantation, and a 500 nm film is coated using a photoresist.
Open a window with a length of 7,000 people from 0 Å (Figure 1 (a)
). Next, a second insulating film 4 made of a different material from the first insulating film 3 is deposited using a multiple deposition method so as to cover the first insulating film 3 and its opening (FIG. 1(b)). , and R
The second insulating film 4 is etched from above using an anisotropic etching method such as the IE method to form an opening approximately 1500 mm in length on the n-layer 1 (FIG. 1(C)). Next, a metal layer 5 is formed by normal vapor deposition of a high melting point metal such as tungsten, and is flattened with a resist 6 (FIG. 1(d)). after that.

The metal layer 5 is formed from above using the RIE method using the resist as a mask.
is etched to form a gate electrode VFA7 (FIG. 1(e)). Then, the first insulating film 3 is removed using a wet etching method, and the gate electrode 7 and the second insulating film 4 are removed.
Ion implantation is performed using the mask as a mask to form impurity regions that will become the source and drain regions, and the n0 layer 8 (Fig. 1(f)).
. Next, the second insulating film 4 is removed by wet etching, and ions are implanted using the gate electrode 7 as a mask.
An intermediate concentration of n that is thinner than M8 and thicker than n layer 1.
'f19 is formed (Fig. 1(g)). Finally, the entire surface is covered with an insulating film 10 and activated by annealing (FIG. 1(h)).

According to the FET of this embodiment configured as described above, by using the multiple deposition method, the gate length can be controlled by the layer thickness of the second insulating film 4, which is layered, and by easy exposure technology. A short gate length of around 1500A can be achieved. Also, L
The DD structure is formed in a self-aligned manner, and short channel effects can also be prevented. Furthermore, since the surface of the substrate is processed by wet etching, which causes less damage, instead of using RIE, which causes more damage, as in the conventional example, there is little deterioration in FET characteristics. Furthermore, both sides of the gate electrode 7 are filled with n' circles except when implanting 9.

Since it is always supported by an insulating film, it has strong mechanical strength, is prevented from falling during the process, and has good stability.

(Effects of the Invention) According to the present invention, a short gate length can be achieved using a simple exposure technique such as photolithography, and an LDD structure that prevents short channel effects can be created without damaging the substrate surface during gate processing. Since it can be formed stably, its practical effects are great.

[Brief explanation of drawings]

FIG. 1 is a process sectional view of a method for manufacturing an FET according to an embodiment of the present invention, and FIG. 2 is a process sectional view of a conventional method for manufacturing an FET. 1... nFt4, 2... Semi-insulating Ga A
s substrate, 3... first insulating film, 4... second insulating film, 5... metal layer, 6... resist,
7... Gate electrode, 8... N4 layer, 9.
...n'' polishing, 10...insulating film.

Claims (1)

[Claims] forming a first film having a desired first opening on the semiconductor conductive layer; and depositing a second film in multiple layers on the first opening and the first film. , etching the second film to provide a second opening smaller than the first opening above the first opening, and forming an electrode using the second opening as a mask. a step of removing the first film and performing ion implantation using the electrode and the second film as a mask to form a first impurity region that will become a source and drain region; step of removing the film and performing ion implantation using the electrode as a mask to form a second impurity region having a higher concentration than the conductive layer and a lower concentration than the first impurity region; 1. A method for manufacturing a field effect transistor, comprising a step of covering with a film, annealing, and activating.