JPS6187379A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the diffusion of ions from the end surface of a gate electrode, and to obtain an element operating at high speed and having low power consumption by applying a film having small implantation stopping power onto an active layer and the surface of a gate electrode and implanting ions while using the film as a mask to form source-drain regions. CONSTITUTION:An active layer 2 is shaped to a semiconductor substrate 1, a Schottky barrier type gate electrode 3 on the active layer is formed, a film 7 having small implantation stopping power is applied onto the active layer 2 and the gate electrode 3, and ions are implanted while employing the film 7 as a mask to shape source-drain regions. A film such as a photo-resist film is used as said film 7 having small implantation stopping power. Consequently, ions are implanted sufficiently up to the central section of a semiconductor through the film thickness of a mask material even when the film thickness of the mask material is thickened while a distance from a gate end is taken in long size because of the thick mask material, thus minimally inhibiting an extent in the lateral direction. Accordingly, a semiconductor device operating at high speed and having low power consumption is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a field effect transistor (FF, T) by self-alignment.

Conventionally, in a self-alignment Schottky barrier type gate electrode FET, the source region and drain region are generally formed by a self-alignment ion implantation method using the gate electrode as a mask.

However, an FB that operates at high speed and with low power consumption
In the T structure, the gate electrode, l, needs to be 1 μm or less, and in this case, in the conventional ion implantation method for forming source and drain electrodes, the ions spread in the lateral direction, causing the threshold voltage to decrease. It is also considered to form an oxide film after forming the gate electrode and use it as a mask for ion implantation, but in this case as well, the lateral spread is suppressed to a certain extent, but the series resistance is There are drawbacks such as an increase in the amount of energy used, and improvement of this is desired.

[Conventional technology]

FIGS. 3fa) to 3(C) show cross-sectional views for explaining a method of manufacturing a Schottky gate field effect transistor using a conventional self-alignment method.

Figure 3 shows activation by injecting silicon ions into the surface of a semi-insulating gallium arsenide (GaAs) substrate l at an acceleration voltage of 60 Kev and a dose of 8xlO''/- as shown by the arrow, and forming an active layer 2. was formed.

For example, tungsten silicide (WS
i) is deposited and dry etched to form the gate electrode 3.
form.

In FIG. 3(C), silicon ions are accelerated at a voltage of 175 KeV and at a dose of 1.8x in a part deeper than the active layer.
Implantation is performed with lO13/, J to form source region 4 and drain region 5.

Figure 4 shows the relationship in which the threshold voltage (Vth) of the FET changes when the gate width is 20 μm and the gate length is changed. However, when the gate length becomes 1 μm or less, vth decreases rapidly, but this is because ion implantation was performed to form the source and drain electrodes, and the influence of the lateral spread of the gate end face becomes stronger. As a result, the effective gate length became extremely shorter than the actual gate length.
h has decreased, and this is due to the strong short gate effect in the FET.

Figure 5 shows the implanted ion concentration using isoconcentration lines when the gate length of the gate electrode 3 is 1 μm and the source 4 and drain 5 regions are formed by implantation using the conventional method. Due to the spread of the ion concentration 1015/c
The effective gate electrode length in the case of the isoconcentration line of I11 is approximately 1 μm, but the effective gate length L is approximately 0.4
It becomes short to μm.

If the implantation conditions are the same, the lateral spread is the same, so when the gate length is 1 μm or less, the effective gate length becomes extremely short.

FIG. 6 shows a method for reducing lateral expansion. After forming the active layer 2 and gate electrode 3 in the same manner as described above, a silicon dioxide film 6 of 1,500 layers is formed and used as an implantation mask. Isoconcentration lines of implanted ions forming the source 4 and drain 5 under implantation conditions are displayed.

From FIG. 6, it can be seen that the ion concentration of 10''/an! penetrates about 0.15 μm from the gate edge, which is about half compared to the method described above, but the implantation in the source 4 and drain 5 regions It has the disadvantage of becoming thinner.

That is, the series resistance increases, and therefore, in this state, there is a problem that a device with high speed operation and low power consumption cannot be obtained.

(Problems to be Solved by the Invention) When ions are implanted to form the active region of the FET having the above structure, diffusion of ions from the end face of the gate electrode is a problem.

[Means for solving problems]

The present invention provides a method for manufacturing a semiconductor device that solves the above problems, and the method includes forming an active layer on a semiconductor substrate, forming a Schottky barrier type gate electrode on the active layer, and then This can be achieved by a method of manufacturing a semiconductor device characterized in that the regions are formed by depositing a film with a low injection blocking ability on the surfaces of the active layer and the gate electrode, and performing ion implantation using the line film as a mask.

[Effect]

In the present invention, instead of using a silicon dioxide film as a mask when performing ion implantation to form the active region of the FET having the above structure, a photoresist with a large Rp is used as a mask film, so that the ion implantation can be performed in the lateral direction. This takes into account a self-alignment FET that minimizes the spread of.

〔Example〕

In the conventional ion implantation method, the gate electrode spreads in the lateral direction, and even when a silicon dioxide mask is used, the spread occurs from the end face of the gate electrode.
If the film thickness of the mask is increased, the lateral expansion of the gate can be suppressed, but as mentioned above, the series resistance of the source and drain regions becomes large. Since the Rp of the semiconductor (referred to as The resistance in the area increases.

Therefore, it is sufficient to use a mask material that has a large Rp compared to the Rp of the semiconductor, and for this purpose, even if the film thickness of the mask material is thick, ions can be sufficiently implanted through the film thickness of the mask material to the center of the semiconductor. On the other hand, an advantage of the thick mask material is that it allows a long distance from the gate edge, so lateral spread can be suppressed to a minimum.

FIG. 1 is a sectional view for explaining the present invention in detail,
FIG. 2 shows isoconcentration lines of implanted ions when ions are implanted using the present invention.

The implantation conditions were the same as above, and a photoresist film was selected as the mask material based on the ratio of Rp of the semiconductor to 5.24.

Therefore, when the photoresist 7 is formed with a mask to a thickness of 3000, as can be seen in FIG. There is almost no difference compared to the conventional method.

Figure 4 shows v when the gate length is changed using the present invention.
The th dependence is indicated by b, and since the effective gate length is longer than in the conventional method, there is no sudden drop in vth.

Figure 2 shows the ratio of Rp between the mask material and the semiconductor on the horizontal axis when the mask thickness of the photoresist film is 3000, and the implantation conditions are the acceleration voltage of 175KeV and the dose of 1.8xlO''/crA as described above. The vertical axis shows the change in Rp and the ratio of change in series resistance when the series resistance of the source and drain regions when implanted without a mask is taken as 100%. It can be seen that the series resistance becomes 90% or more, and the optimum Rp ratio is 5 or more.

〔Effect of the invention〕

As described in detail above, by employing the manufacturing method of the present invention, there is a great effect that a semiconductor device with high speed operation and low power consumption can be provided.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view for explaining the ion implantation method of the present invention, Fig. 2 is a diagram of the relationship between Rp and series resistance, Fig. 3 is a cross-sectional view for explaining the conventional manufacturing method, Fig. 4 is a relationship diagram between gate length and threshold voltage, Figure 5.
FIG. 6 is a cross-sectional view for explaining the conventional ion implantation method. In the figure, 1 is a semi-insulating substrate, 2 is an active region. 3 is a gate electrode, 4 is a source region, 5 is a drain region,
Reference numeral 6 indicates a silicon dioxide film, and reference numeral 7 indicates a photoresist film. Figure 1 Figure 2 Rp ratio Figure 3 Figure 4 Flash length (pm) Figure 5 Figure 6 Ryl

Claims (3)

[Claims] (1) After forming an active layer on a semiconductor substrate and forming a Schottky barrier type gate electrode on the active layer, a film with low injection blocking ability is deposited on the surfaces of the active layer and gate electrode. , Ion implantation is performed using the film as a mask to form a source,
A method of manufacturing a semiconductor device, comprising forming a drain region. (2) In the method for manufacturing a semiconductor device, when forming a submicron gate length, the ratio of the ion average projected range of the film covering the surfaces of the active layer and gate electrode to that of the semiconductor substrate is 5 or more. A method for manufacturing a semiconductor device according to claim 1, characterized in that: (3) The method for manufacturing a semiconductor device according to claim 1, wherein a photoresist film is used as the film having a small injection blocking ability.