JPS5830162A - 電極の形成方法 - Google Patents

電極の形成方法

Info

Publication number
JPS5830162A
JPS5830162A JP57131337A JP13133782A JPS5830162A JP S5830162 A JPS5830162 A JP S5830162A JP 57131337 A JP57131337 A JP 57131337A JP 13133782 A JP13133782 A JP 13133782A JP S5830162 A JPS5830162 A JP S5830162A
Authority
JP
Japan
Prior art keywords
silicon
layer
silicide
polycrystalline silicon
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57131337A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0234455B2 (https=
Inventor
ヘンリ−・ジヨン・ゲイペル・ジユニア
ニング・シ−
チヤ−ルズ・ウイリアム・コバ−ガ−・サ−ド
ラリ−・アラン・ネスビツト
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5830162A publication Critical patent/JPS5830162A/ja
Publication of JPH0234455B2 publication Critical patent/JPH0234455B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/01312—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H10W20/066—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by forming silicides of refractory metals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP57131337A 1981-07-30 1982-07-29 電極の形成方法 Granted JPS5830162A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/288,608 US4389257A (en) 1981-07-30 1981-07-30 Fabrication method for high conductivity, void-free polysilicon-silicide integrated circuit electrodes
US288608 1988-12-22

Publications (2)

Publication Number Publication Date
JPS5830162A true JPS5830162A (ja) 1983-02-22
JPH0234455B2 JPH0234455B2 (https=) 1990-08-03

Family

ID=23107854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57131337A Granted JPS5830162A (ja) 1981-07-30 1982-07-29 電極の形成方法

Country Status (4)

Country Link
US (1) US4389257A (https=)
EP (1) EP0071029B1 (https=)
JP (1) JPS5830162A (https=)
DE (1) DE3277753D1 (https=)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3211752C2 (de) * 1982-03-30 1985-09-26 Siemens AG, 1000 Berlin und 8000 München Verfahren zum selektiven Abscheiden von aus Siliziden hochschmelzender Metalle bestehenden Schichtstrukturen auf im wesentlichen aus Silizium bestehenden Substraten und deren Verwendung
US4569122A (en) * 1983-03-09 1986-02-11 Advanced Micro Devices, Inc. Method of forming a low resistance quasi-buried contact
JPS59210642A (ja) * 1983-05-16 1984-11-29 Hitachi Ltd 半導体装置の製造方法
US4470189A (en) * 1983-05-23 1984-09-11 International Business Machines Corporation Process for making polycide structures
DE3326142A1 (de) * 1983-07-20 1985-01-31 Siemens AG, 1000 Berlin und 8000 München Integrierte halbleiterschaltung mit einer aus aluminium oder aus einer aluminiumlegierung bestehenden aeusseren kontaktleiterbahnebene
JPS6063926A (ja) * 1983-08-31 1985-04-12 Fujitsu Ltd 半導体装置の製造方法
US4716131A (en) * 1983-11-28 1987-12-29 Nec Corporation Method of manufacturing semiconductor device having polycrystalline silicon layer with metal silicide film
US4640844A (en) * 1984-03-22 1987-02-03 Siemens Aktiengesellschaft Method for the manufacture of gate electrodes formed of double layers of metal silicides having a high melting point and doped polycrystalline silicon
US4612258A (en) * 1984-12-21 1986-09-16 Zilog, Inc. Method for thermally oxidizing polycide substrates in a dry oxygen environment and semiconductor circuit structures produced thereby
US4803539A (en) * 1985-03-29 1989-02-07 International Business Machines Corporation Dopant control of metal silicide formation
US4660276A (en) * 1985-08-12 1987-04-28 Rca Corporation Method of making a MOS field effect transistor in an integrated circuit
US4663191A (en) * 1985-10-25 1987-05-05 International Business Machines Corporation Salicide process for forming low sheet resistance doped silicon junctions
JPH0616556B2 (ja) * 1987-04-14 1994-03-02 株式会社東芝 半導体装置
US4933994A (en) * 1987-06-11 1990-06-19 General Electric Company Method for fabricating a self-aligned lightly doped drain semiconductor device with silicide
EP0327210A1 (en) * 1988-01-20 1989-08-09 Advanced Micro Devices, Inc. Method of preventing silicide peel-off
GB2222416B (en) * 1988-08-31 1993-03-03 Watkins Johnson Co Processes using disilane
US4992391A (en) * 1989-11-29 1991-02-12 Advanced Micro Devices, Inc. Process for fabricating a control gate for a floating gate FET
KR920015622A (ko) * 1991-01-31 1992-08-27 원본미기재 집적 회로의 제조방법
US6284584B1 (en) * 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
US5804499A (en) * 1996-05-03 1998-09-08 Siemens Aktiengesellschaft Prevention of abnormal WSix oxidation by in-situ amorphous silicon deposition
GB2319658B (en) * 1996-09-21 2001-08-22 United Microelectronics Corp Method of fabricating a word line
DE19742972A1 (de) * 1997-09-29 1999-04-08 Siemens Ag Verfahren zur Ausbildung eines niederohmigen Leitbahnbereichs auf einem Halbleitersubstrat
DE10121240C1 (de) * 2001-04-30 2002-06-27 Infineon Technologies Ag Verfahren zur Herstellung für eine integrierte Schaltung, insbesondere eine Anti-Fuse, und entsprechende integrierte Schaltung
US6630394B2 (en) * 2001-12-28 2003-10-07 Texas Instruments Incorporated System for reducing silicon-consumption through selective deposition
KR100558284B1 (ko) * 2003-12-24 2006-03-10 한국전자통신연구원 폴리실리콘층의 결정화/활성화 방법 및 이를 이용한폴리실리콘 박막트랜지스터 제조방법
US20060079075A1 (en) * 2004-08-12 2006-04-13 Lee Chang-Won Gate structures with silicide sidewall barriers and methods of manufacturing the same
JP4969779B2 (ja) * 2004-12-28 2012-07-04 株式会社東芝 半導体装置の製造方法
JP4690120B2 (ja) * 2005-06-21 2011-06-01 エルピーダメモリ株式会社 半導体装置及びその製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5441087A (en) * 1977-09-07 1979-03-31 Nec Corp Semiconductor integrated circuit device
JPS5469972A (en) * 1977-11-11 1979-06-05 Ibm Method of fabricating conductive polysilicon and silicon metal coupling structure

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3381182A (en) * 1964-10-19 1968-04-30 Philco Ford Corp Microcircuits having buried conductive layers
US3881971A (en) * 1972-11-29 1975-05-06 Ibm Method for fabricating aluminum interconnection metallurgy system for silicon devices
US3911168A (en) * 1973-06-01 1975-10-07 Fairchild Camera Instr Co Method for forming a continuous layer of silicon dioxide over a substrate
US4152823A (en) * 1975-06-10 1979-05-08 Micro Power Systems High temperature refractory metal contact assembly and multiple layer interconnect structure
US4180596A (en) * 1977-06-30 1979-12-25 International Business Machines Corporation Method for providing a metal silicide layer on a substrate
US4332839A (en) * 1978-12-29 1982-06-01 Bell Telephone Laboratories, Incorporated Method for making integrated semiconductor circuit structure with formation of Ti or Ta silicide
US4228212A (en) * 1979-06-11 1980-10-14 General Electric Company Composite conductive structures in integrated circuits
GB2077993A (en) * 1980-06-06 1981-12-23 Standard Microsyst Smc Low sheet resistivity composite conductor gate MOS device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5441087A (en) * 1977-09-07 1979-03-31 Nec Corp Semiconductor integrated circuit device
JPS5469972A (en) * 1977-11-11 1979-06-05 Ibm Method of fabricating conductive polysilicon and silicon metal coupling structure

Also Published As

Publication number Publication date
EP0071029A2 (en) 1983-02-09
JPH0234455B2 (https=) 1990-08-03
US4389257A (en) 1983-06-21
DE3277753D1 (en) 1988-01-07
EP0071029B1 (en) 1987-11-25
EP0071029A3 (en) 1984-12-27

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