JPS5826536Y2 - 積層型半導体装置 - Google Patents

積層型半導体装置

Info

Publication number
JPS5826536Y2
JPS5826536Y2 JP1977064248U JP6424877U JPS5826536Y2 JP S5826536 Y2 JPS5826536 Y2 JP S5826536Y2 JP 1977064248 U JP1977064248 U JP 1977064248U JP 6424877 U JP6424877 U JP 6424877U JP S5826536 Y2 JPS5826536 Y2 JP S5826536Y2
Authority
JP
Japan
Prior art keywords
semiconductor device
external terminals
semiconductor
external
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1977064248U
Other languages
English (en)
Japanese (ja)
Other versions
JPS53159273U (enExample
Inventor
秀明 下田
栄造 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1977064248U priority Critical patent/JPS5826536Y2/ja
Publication of JPS53159273U publication Critical patent/JPS53159273U/ja
Application granted granted Critical
Publication of JPS5826536Y2 publication Critical patent/JPS5826536Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP1977064248U 1977-05-18 1977-05-18 積層型半導体装置 Expired JPS5826536Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1977064248U JPS5826536Y2 (ja) 1977-05-18 1977-05-18 積層型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1977064248U JPS5826536Y2 (ja) 1977-05-18 1977-05-18 積層型半導体装置

Publications (2)

Publication Number Publication Date
JPS53159273U JPS53159273U (enExample) 1978-12-13
JPS5826536Y2 true JPS5826536Y2 (ja) 1983-06-08

Family

ID=28968194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1977064248U Expired JPS5826536Y2 (ja) 1977-05-18 1977-05-18 積層型半導体装置

Country Status (1)

Country Link
JP (1) JPS5826536Y2 (enExample)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5036281Y2 (enExample) * 1971-07-26 1975-10-22
JPS589585B2 (ja) * 1974-10-04 1983-02-22 日本電気株式会社 デンシブヒンヨウリ−ドフレ−ム

Also Published As

Publication number Publication date
JPS53159273U (enExample) 1978-12-13

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