JPS58201121A - 遅延時間補正方式 - Google Patents

遅延時間補正方式

Info

Publication number
JPS58201121A
JPS58201121A JP57083024A JP8302482A JPS58201121A JP S58201121 A JPS58201121 A JP S58201121A JP 57083024 A JP57083024 A JP 57083024A JP 8302482 A JP8302482 A JP 8302482A JP S58201121 A JPS58201121 A JP S58201121A
Authority
JP
Japan
Prior art keywords
correction
circuit
time
delay
delay time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57083024A
Other languages
English (en)
Japanese (ja)
Other versions
JPH034925B2 (enrdf_load_stackoverflow
Inventor
Takashi Matsumoto
隆 松本
Akira Yamagiwa
明 山際
Ryozo Yoshino
亮三 吉野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57083024A priority Critical patent/JPS58201121A/ja
Publication of JPS58201121A publication Critical patent/JPS58201121A/ja
Publication of JPH034925B2 publication Critical patent/JPH034925B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Pulse Circuits (AREA)
JP57083024A 1982-05-19 1982-05-19 遅延時間補正方式 Granted JPS58201121A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57083024A JPS58201121A (ja) 1982-05-19 1982-05-19 遅延時間補正方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57083024A JPS58201121A (ja) 1982-05-19 1982-05-19 遅延時間補正方式

Publications (2)

Publication Number Publication Date
JPS58201121A true JPS58201121A (ja) 1983-11-22
JPH034925B2 JPH034925B2 (enrdf_load_stackoverflow) 1991-01-24

Family

ID=13790664

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57083024A Granted JPS58201121A (ja) 1982-05-19 1982-05-19 遅延時間補正方式

Country Status (1)

Country Link
JP (1) JPS58201121A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01216274A (ja) * 1988-02-25 1989-08-30 Fujitsu Ltd Lsi試験装置
US6784684B2 (en) 2001-09-25 2004-08-31 Renesas Technology Corp. Testing apparatus including testing board having wirings connected to common point and method of testing semiconductor device by composing signals

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS524751A (en) * 1975-06-27 1977-01-14 Ibm Automatic clock control system
JPS55960A (en) * 1978-06-20 1980-01-07 Fujitsu Ltd Clock distributor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS524751A (en) * 1975-06-27 1977-01-14 Ibm Automatic clock control system
JPS55960A (en) * 1978-06-20 1980-01-07 Fujitsu Ltd Clock distributor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01216274A (ja) * 1988-02-25 1989-08-30 Fujitsu Ltd Lsi試験装置
US6784684B2 (en) 2001-09-25 2004-08-31 Renesas Technology Corp. Testing apparatus including testing board having wirings connected to common point and method of testing semiconductor device by composing signals

Also Published As

Publication number Publication date
JPH034925B2 (enrdf_load_stackoverflow) 1991-01-24

Similar Documents

Publication Publication Date Title
JP3453133B2 (ja) Ic試験装置のタイミング校正方法及びその校正方法を用いた校正機能を有するic試験装置
EP0356967B1 (en) Pin electronics device having a phase adjustment function for IC testers and phase adjustment method therefor
US7782064B2 (en) Test apparatus and test module
JPS60247942A (ja) 半導体メモリ試験装置
WO2007049476A1 (ja) 試験装置、及び試験方法
US5463639A (en) Automatic pattern synchronizing circuit of an error detector
JP2608167B2 (ja) Icテスタ
JPS58201121A (ja) 遅延時間補正方式
US20090105977A1 (en) Test apparatus, skew measuring apparatus, device and board
WO2004038436A1 (ja) 目標値の探索回路、目標値の探索方法及びこれを用いた半導体試験装置
US7733113B2 (en) Semiconductor test device
JPH09197010A (ja) Ic試験装置の伝搬遅延時間の補正方法
JPH02198375A (ja) Ic試験装置
JP2002156414A (ja) タイミング校正機能を具備した半導体デバイス試験装置
JP4502448B2 (ja) Ic試験装置における電圧発生器の校正方法・電圧発生器の校正装置
JP4900031B2 (ja) 半導体試験装置
JPH0736300Y2 (ja) タイミング校正装置
JP2011095079A (ja) 半導体試験装置
JPS61286768A (ja) テスト装置
JP2000180514A (ja) タイミング校正方法、タイミング校正装置及びこのタイミング校正装置を備えたic試験装置
JPH10232268A (ja) 半導体試験装置用比較電圧源
JP2002257901A (ja) スキュータイミング調整装置および方法
JPH09166649A (ja) Icテストシステムにおけるi/oピン測定方法
JPH0778518B2 (ja) Icテスト装置
JPH11337618A (ja) タイミング・デスキュー装置及びタイミング・デスキュー方法