JPS58184733A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58184733A
JPS58184733A JP6829882A JP6829882A JPS58184733A JP S58184733 A JPS58184733 A JP S58184733A JP 6829882 A JP6829882 A JP 6829882A JP 6829882 A JP6829882 A JP 6829882A JP S58184733 A JPS58184733 A JP S58184733A
Authority
JP
Japan
Prior art keywords
substrate
element substrate
semiconductor device
supporting substrate
support
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6829882A
Other languages
Japanese (ja)
Inventor
Yoshimasa Kudo
工藤　好正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6829882A priority Critical patent/JPS58184733A/en
Publication of JPS58184733A publication Critical patent/JPS58184733A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

PURPOSE:To mitigate a warp to be generated in the element substrate of a semiconductor device by a method wherein a supporting substrate to be fixed with a semiconductor integrated circuit element is divided into two pieces, and the element is adhered thereon. CONSTITUTION:In a supporting substrate 11, an isolation strip 11a is formed in parallel with one side thereof. An element substrate 3 is joined on such the supporting substrate 11 interposing a junction member 2 between them. At this time, a part or the whole of the isolation strip 11a is made to be positioned at the lower side of the element substrate 3. Accordingly, one side of the supporting substrate 11 becomes as the free edge, and an influence of the supporting substrate 11 to the element substrate 3 to be joined is reduced extremely. Especially, because the bimetal effect is negated, the warp of the joined element substrate 3 is eliminated, and the characteristic is stabilized extremely.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は支持基板に素子基板が取り付けられている半
導体装置に関する、 〔発明の技術的背景〕 第１回置（トに従来の支持基板に対する素子基板の取り
付は方法な示す。なお、第１回置はその平面図であり、
同図田）は同図（３）のｘ−ｘ’におけるＩＩＴ面図で
ある。図中、１は支持基板１示している。この支持基板
１１には接合部材２ｖ介して素子基板３が接合されてい
る。このとき。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device in which an element substrate is attached to a support substrate. The method for mounting the board is shown below.The first location is a plan view.
Figure 3) is an IIT plane view taken along line xx' in Figure (3). In the figure, 1 indicates a support substrate 1. The element substrate 3 is bonded to this support substrate 11 via a bonding member 2v. At this time.

素子基１１！、ｍ合部材２％支持基板Ｉはそれぞれの素
材の線膨張係数、ヤング率等がそれぞれ異なるために素
子基板３には、接合温度と実使用湿度との差により歪が
生じる。この素子基板３に生じる企は、素子基板３．接
合部材２．支持基板１０１ｖＥ材の線膨張係数の差が小
さい径小さい率は明らかである、。Element group 11! , m composite member 2% supporting substrate I has different coefficients of linear expansion, Young's modulus, etc. of each material, so distortion occurs in the element substrate 3 due to the difference between the bonding temperature and the actual humidity. The problem occurring on the element substrate 3 is the element substrate 3. Joining member 2. It is clear that the smaller the difference in linear expansion coefficient of the supporting substrate 101vE material, the smaller the diameter.

〔背ｌ１１−技鉤の問題点〕 したがって、従来より上記の串Ｖ考慮して。[Back l11-Problems with Waza hook] Therefore, considering the above skewer V than before.

支持基板ｌの素材として線膨張係数が素子基板３に近い
４２１０イ、１パール等が用いられてきた。しかしなが
ら、これらの材料は熱伝導率が小さく、素子基板３が取
り付けられた支持基板１ｖ樹脂封止した場合には、熱抵
抗が大きくなってしまう、そこで、熱抵抗を小さくする
ために、熱伝導率の大きい銅系の素材を用いることが考
えられるが、銅系の素材は線膨張係数が大きいため、素
子基板内に生じる歪が大きくなり、最悪９）場合には素
子基板に割れが生じてしまう、 第１表には各撞素材の諸性質および樹脂封止した場合の
熱抵抗の一例を示す。As the material for the support substrate 1, materials such as 4210I and 1Pearl, which have linear expansion coefficients close to those of the element substrate 3, have been used. However, these materials have low thermal conductivity, and when the supporting substrate 1v to which the element substrate 3 is attached is sealed with resin, the thermal resistance becomes large. It is possible to use a copper-based material with a high coefficient of thermal expansion, but since copper-based materials have a large coefficient of linear expansion, the strain that occurs within the element substrate becomes large, and in the worst case 9), the element substrate may crack. Table 1 shows an example of the properties of each elastic material and the thermal resistance when resin-sealed.

第１表 たとえば、４２７０イＶ素材とした支持基板ｌｒｍｆ用
いた場合、素子基板３との間に生じる変形が、！Ｊ２図
囚装置す程度であるとでると。Table 1 For example, when a supporting substrate lrmf made of 4270V material is used, the deformation that occurs between it and the element substrate 3 is ! It appears that it is only a J2 figure prisoner device.

銅系素材の支持基１１１１１ｂを用いた場合の素子幕板
３との間に生じる変形は、第２図旧）に示すようになる
。丁なわち、銅系素材の支持基板１を用いた場合の方が
より大きな変形を生じる。When the supporting base 11111b made of a copper-based material is used, the deformation that occurs between the supporting base 11111b and the element curtain plate 3 is as shown in FIG. 2 (old). In other words, larger deformation occurs when the supporting substrate 1 is made of a copper-based material.

なお、素子基板３には線膨張差（：よる収縮と）（イメ
タル効果による反りが生じる、 第２表は、３１１ｊ［−’の素子基板を４２１０イある
いは燐脱酸銅を素材とした支持基板に、各種接着材料を
用いて接着した時に、素子基板表面に生じる応力の大き
さを示している。なお、この表において、十は引張応力
を示し、−は圧縮応力を示している。Note that the element substrate 3 is warped due to linear expansion difference (: shrinkage) (Imetal effect).Table 2 shows that the element substrate of 311j [-' 2 shows the magnitude of stress generated on the surface of the element substrate when bonded using various adhesive materials. In this table, 10 indicates tensile stress, and - indicates compressive stress.

１） 第２表 単位に／ｃｄ 〔発すの目的〕 この発明は上記の点に鑑みてなされたもので。1) Table 2 unit/cd [Purpose of emitting] This invention was made in view of the above points.

その目的は素子基板を支持基板に取り付けたときの素子
基板に生じる企を緩和することができる半導体装Ｗｔｖ
提供することにある。The purpose is to reduce the damage caused to the element substrate when the element substrate is attached to the support substrate.
It is about providing.

〔発明の概要〕[Summary of the invention]

半導体集積回路素子、その素子基板を取りつける支持基
板及び上記素子の電気的入出力となるリード部を設けそ
れらを樹脂封止してなる半導体装置において、支持基板
が２つに分離されその分離体をまたがり２つの支持基板
に少くとも一ケ所あるいは全面に上記素子が接着されて
いる。In a semiconductor device in which a semiconductor integrated circuit element, a support substrate to which the element substrate is mounted, and lead portions for electrical input and output of the element are provided and sealed with resin, the support substrate is separated into two parts, and the separated body is The above-mentioned element is bonded to at least one place or the entire surface of the two supporting substrates.

〔発明の実施例〕[Embodiments of the invention]

以下１図面を参照してこの発明の一実施例を説明する。 An embodiment of the present invention will be described below with reference to one drawing.

第８図はこの発明の一実施例の支持基板の平面図である
。丁なわち、長方形状の銅系材料からなる支持基Ｉｌｌ
目；は、その１辺に平行な分離体１１−が形成されてい
る。このように形成された支持基＄１１上に１ｍ合部材
（接着部材）を介して図示せぬ素子基板が接合される。FIG. 8 is a plan view of a support substrate according to an embodiment of the present invention. In other words, a rectangular supporting base Ill made of a copper-based material.
A parallel separation body 11- is formed on one side of the eye. An element substrate (not shown) is bonded onto the support base $11 thus formed via a 1 m bonding member (adhesive member).

このとき、素子基板の下面に上記分離体１１ｍの一部あ
るいは全部が位ＩＴるように５ｆ−ることか肝要である
。そして１例えばこのよう４＝支持基板１１に取り付け
られた素子基板の複数の電極と図示せぬ各インナーリー
ドとをワイヤ接続したリードフレームの樹脂封止を行な
う。At this time, it is important that part or all of the separator 11m be placed on the lower surface of the element substrate. Then, a lead frame in which a plurality of electrodes of the element substrate attached to the support substrate 11 and each inner lead (not shown) are connected by wire is sealed with resin.

したがって、このような半導体装置では、支持＆１ｋＩ
Ｉが片方自由端となり、接合される素子基板に対する支
持基板１１の影舎は極めて小さくなる。特に、バイメタ
ル効果がなくなるため（＝、接合された素子基板の反り
がなくなり。Therefore, in such a semiconductor device, support & 1kI
I becomes one free end, and the shadow of the support substrate 11 relative to the element substrate to be bonded becomes extremely small. In particular, since the bimetal effect disappears (=, the warpage of the bonded element substrate disappears).

橋めて安定した特性を出すことができる。また、支持基
板の素材として銅系の材料を用いているため、熱抵抗を
低下させることができる。It can be bridged to produce stable characteristics. Furthermore, since a copper-based material is used as the material for the support substrate, thermal resistance can be reduced.

第４図はこの発明の他の実施例の支持基板の平面図であ
る。すなわち、長方形状の１１Ｍ材料からなる支持基板
１２には、図示されるような蛇行状の切り込み１２１１
が形成されている。そして、Ａｉｌ記実施例と同様に、
この支持基板１２上に接合部ｚ′？介して素子基板が接
合される。FIG. 4 is a plan view of a support substrate according to another embodiment of the invention. That is, the rectangular support substrate 12 made of 11M material has meandering cuts 1211 as shown in the figure.
is formed. And, similar to the example described in Ail,
On this support substrate 12 is a joint z'? The element substrate is bonded through the substrate.

この場合にも、前記実施例と同様な効果を得ることがで
きる。In this case as well, the same effects as in the embodiment described above can be obtained.

第５図は絶縁性材料１４を支持幕板１１の下面に接着し
たよってを示す断面図である。このように、絶縁性材料
Ｉ４を分離体１１Ｍにはることにより、マウント時のマ
ウント材の分離体１１−からの漏れを防ぐことが□・で
きる。また。FIG. 5 is a sectional view showing the insulating material 14 bonded to the lower surface of the support curtain plate 11. As shown in FIG. In this way, by applying the insulating material I4 to the separator 11M, it is possible to prevent the mounting material from leaking from the separator 11- during mounting. Also.

支持基板１１はフレーム枠より所定幅で支持されている
が、９蝋されることにより、片持ちはりとなる。このた
め、若干上下の変形要因となるためその補助効果の役割
りもしている。また、上記絶縁性材料１４は耐熱性があ
り、熱による支持基板の変形に追従して変形するような
ものが望ましい。The support substrate 11 is supported by a predetermined width from the frame, and becomes a cantilever beam by being soldered. For this reason, it becomes a factor of slight vertical deformation, and also serves as an auxiliary effect. Further, the insulating material 14 is preferably heat resistant and deforms following the deformation of the support substrate due to heat.

ところで、フラットパック形パッケージにおいてはリー
ド部材と樹脂との線膨張係数の相違によりリードと樹脂
との間に間隙が生じることを防上することかできるので
耐湿性の問題を解消することができる。By the way, in a flat pack type package, it is possible to prevent a gap from forming between the lead and the resin due to the difference in linear expansion coefficient between the lead member and the resin, so that the problem of moisture resistance can be solved.

〔発明の効果〕〔Effect of the invention〕

以上詳述したようにこの発明によれば、素子基板を支持
基板に取り付けたときの素子基板に生じる歪を緩和させ
ることができる半導体Ｖｔ１ｌを提供することができる
。As described in detail above, according to the present invention, it is possible to provide a semiconductor Vt1l that can alleviate the strain that occurs in the element substrate when the element substrate is attached to the support substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

第１因囚は従来の半導体装置の平面図、第１図（Ｂｌは
第１図（Ａｌｅおけ１１ろｘ−ｘ’における断面図、第
２図（Ａｔ　ｆＢｌはそれぞれ支持基板（＝異なった材
料を用いた場合の変形を示す図、第３図はこの発明の一
実施例Ｃ二おける支持基板の平面図。 第４図はこの発明の他の実施例の支持＆蓼の平面図、第
５図は絶縁性材料を支持基板の下面６＝接着したようす
を示す断１ｉｉｌｉ＠Ｉである。 １．１１．１２・・・支持基板、２・・・接金部材。 ３・・・素子基板、１１■・・・分離体、１４・・・絶
縁性材料。 出顧人代理人　弁理士　　鈴　　江　武　　廖第１図 （Ａ） （Ｂ） 第２図 （Ａ）　　　　　　（Ｂ）The first factor is the plan view of a conventional semiconductor device, Figure 1 (Bl is a cross-sectional view at Figure 3 is a plan view of the support substrate in Embodiment C2 of the present invention. Figure 4 is a plan view of the support and sole of another embodiment of the present invention. The figure is a cross section 1iii@I showing how the insulating material is bonded to the lower surface 6 of the support substrate. 1.11.12... Support substrate, 2... Welding member. 3... Element substrate, 11■...Separated body, 14...Insulating material. Client agent Patent attorney Suzu Jiang Wu Liao Figure 1 (A) (B) Figure 2 (A) (B)

Claims (1)

【特許請求の範囲】 ｔｌｌ　　半導体集積回路素子、その素子基板を取りつ
ける支持基板及び上記素子の電気的入出力となるリード
部を設けそれらを樹脂封止してなる半導体装置において
、上記支持基板が２つに分離され、その分離体をまたが
り２つの支持基板に少くとも一ケ所、あるいは全面に上
記素子が接着されていることを特徴とする半導体装置。 （２１上記支持基板は下面に分離体を含む少なくとも１
ケ所あるいは全面に絶縁性材料が接着され、上記支持基
板の上面に素子が実装されていることを特徴とする特許
請求の範囲第１項記載の半導体装置。[Scope of Claims] tll A semiconductor device comprising a semiconductor integrated circuit element, a supporting substrate to which the element substrate is attached, and a lead portion for electrical input/output of the element and sealed with a resin, wherein the supporting substrate has two parts. 1. A semiconductor device, characterized in that the device is separated into two parts, and the above-mentioned element is bonded to two support substrates at least in one place or over the entire surface of the two support substrates across the separated parts. (21) The support substrate includes at least one separator on the lower surface.
2. The semiconductor device according to claim 1, wherein an insulating material is adhered to some or all of the support substrate, and an element is mounted on the upper surface of the support substrate.
JP6829882A 1982-04-23 1982-04-23 Semiconductor device Pending JPS58184733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6829882A JPS58184733A (en) 1982-04-23 1982-04-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6829882A JPS58184733A (en) 1982-04-23 1982-04-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58184733A true JPS58184733A (en) 1983-10-28

Family

ID=13369731

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6829882A Pending JPS58184733A (en) 1982-04-23 1982-04-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58184733A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009253153A (en) * 2008-04-09 2009-10-29 Asmo Co Ltd Resin seal type semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009253153A (en) * 2008-04-09 2009-10-29 Asmo Co Ltd Resin seal type semiconductor device

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