JPS63302542A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63302542A JPS63302542A JP13836687A JP13836687A JPS63302542A JP S63302542 A JPS63302542 A JP S63302542A JP 13836687 A JP13836687 A JP 13836687A JP 13836687 A JP13836687 A JP 13836687A JP S63302542 A JPS63302542 A JP S63302542A
- Authority
- JP
- Japan
- Prior art keywords
- insulating resin
- chip
- insulating
- active surface
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000011347 resin Substances 0.000 claims abstract description 43
- 229920005989 resin Polymers 0.000 claims abstract description 43
- 239000004020 conductor Substances 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims abstract description 5
- 230000008602 contraction Effects 0.000 abstract description 9
- 238000005336 cracking Methods 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 238000000465 moulding Methods 0.000 abstract description 3
- 238000007639 printing Methods 0.000 abstract description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体素子（以下ＩＣチップと称する）をイ
ンナーリードポンディングした半導体装置のモールド構
造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mold structure for a semiconductor device in which a semiconductor element (hereinafter referred to as an IC chip) is bonded by inner leads.
従来のＩＣチップをインナーリードポンディングした半
導体装置のモールド構造は、第４図に示すごと＜、ＩＣ
チップ１の能動面５、および側面６をエポキシ、シリコ
ン等の絶縁性樹脂４によりモールドする構造が一般的で
あった。中には、図示しないがＩＣチップの能動面のみ
モールドしたり、またＩＣチップの裏面までモールドす
るものもあった。The mold structure of a conventional semiconductor device using inner lead bonding of an IC chip is shown in Figure 4.
Generally, the active surface 5 and side surface 6 of the chip 1 are molded with an insulating resin 4 such as epoxy or silicon. In some cases, although not shown, only the active surface of the IC chip is molded, and in some cases, the back surface of the IC chip is also molded.
（発明が解決しようとする問題点〕
しかし、前述の従来技術では、半導体装置の使用温度変
化、特に半導体装置を、回路基板にリフロー等の方法で
半田付けする際の熱変化により、ＩＣチップをモールド
している絶縁性樹脂の伸縮によってイ／ナーリードポン
ディジグ部が断線したり、ＩＣチップ自体が割れてしま
う等の問題点があった。また、特にＩＣチップの側面を
モールドする場合には、ＩＣチップ面より突出している
リードに絶縁性樹脂の伸縮による応力が直接前わるため
、更にリードの断線が起きやすいという問題点があった
。(Problems to be Solved by the Invention) However, in the above-mentioned conventional technology, the IC chip is damaged due to changes in the operating temperature of the semiconductor device, especially thermal changes when the semiconductor device is soldered to a circuit board by a method such as reflow. There have been problems such as the expansion and contraction of the insulating resin used in the molding, which can cause wire breakage at the input/inner lead pond jig and the IC chip itself.Also, especially when molding the sides of the IC chip, However, since the stress caused by the expansion and contraction of the insulating resin is directly applied to the leads protruding from the surface of the IC chip, there is a problem in that the leads are more likely to break.
そこで本発明はこのような問題点を解決するもので、そ
の目的とするところは温度変化による絶縁性樹脂の伸縮
、特にＩＣチップから外側にある絶縁性樹脂の伸縮を抑
制し、ＩＣチップ割れや断線のない信頼性の高い半導体
装置のモールド構造を提供するところにある。The present invention is intended to solve these problems, and its purpose is to suppress the expansion and contraction of the insulating resin due to temperature changes, especially the expansion and contraction of the insulating resin outside the IC chip, thereby preventing IC chip cracking. The object of the present invention is to provide a highly reliable mold structure for a semiconductor device without disconnection.
本発明の半導体装置は、樹脂等からなる絶縁板の開口部
に突出する導体リードにインナーリードボンディングさ
れる半導体素子の少なくとも能動面および前記開口部周
囲の前記絶縁板が、絶縁性樹脂によりモールドされてな
る半導体装置において、前記間口部より大きい外形をな
しかつ前記絶縁性樹脂よりも低い熱膨張率を存する材質
の薄板を、前記半導体素子の能動面側に前記絶縁性樹脂
をはさみ込むような形で設け、ことに前記薄板は少なく
とも前記半導体素子のポンディング部から前記絶縁性樹
脂の外縁近傍を覆うことを特徴とする。In the semiconductor device of the present invention, at least the active surface of a semiconductor element that is inner lead-bonded to a conductor lead protruding into an opening of an insulating plate made of resin or the like and the insulating plate around the opening are molded with an insulating resin. In the semiconductor device, the insulating resin is sandwiched between the active surface side of the semiconductor element and a thin plate made of a material having a larger outer diameter than the frontage portion and having a coefficient of thermal expansion lower than that of the insulating resin. In particular, the thin plate covers at least the vicinity of the outer edge of the insulating resin from the bonding portion of the semiconductor element.
以下、本発明について、実施例に基づき詳細に説明する
。Hereinafter, the present invention will be described in detail based on examples.
第１図は本発明の実施例に右ける半導体装置の断面図で
ある。ＩＣチップ１はテープキャリア２０４体リード３
にインナーリードボンディングされており、更にポンデ
ィング部の保護、ＩＣの耐湿性の向上等の目的からエポ
キシ、シリコン等の絶縁性樹脂４で、その能動面５、お
よび側面６がモールドされている。この場合、絶縁性樹
脂４はその流動性によりテープキャリア２の開口部７の
周囲のポリイミド等からなる絶縁板８もモールドするこ
とになる。一方ＩＣチップ１の能動面５側には、薄板９
が絶縁性樹脂４をはさみ込む形で配置されている。上述
のような構造は、ＩＣチップとその周囲にＩＣチップの
能動面５側より、印刷もしくはディスペンサーによる吐
出により絶縁性樹脂４を塗布し、次いで薄板９を載せ軽
（加圧して絶縁性樹脂４を加熱硬化することにより得ら
れる。ここで用いられる薄板９は、絶縁性樹脂４よりも
熱膨張率の小さい、ガラス、セラミックや金属板等であ
り、金属板の場合は短絡を防ぐため、必要に応じて表面
に絶縁処理を施す、薄板８の厚さは材質により異なるが
、絶縁性樹脂４の温度変化による伸縮で変形、破損しな
い程度の厚さで、通常５０〜３００μｍ位とする。また
その大きさは、絶縁板８の開口部７の周囲に広がる絶縁
性樹脂４の面積とほぼ同等とする。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. IC chip 1 has 204 tape carriers and leads 3
The active surface 5 and side surfaces 6 are molded with an insulating resin 4 such as epoxy or silicone for the purpose of protecting the bonding portion and improving moisture resistance of the IC. In this case, the insulating resin 4 also molds the insulating plate 8 made of polyimide or the like around the opening 7 of the tape carrier 2 due to its fluidity. On the other hand, a thin plate 9 is provided on the active surface 5 side of the IC chip 1.
are arranged to sandwich the insulating resin 4. The above-mentioned structure is made by applying insulating resin 4 to the IC chip and its surroundings from the active surface 5 side of the IC chip by printing or discharging from a dispenser, and then placing a thin plate 9 on the insulating resin 4 by applying pressure. The thin plate 9 used here is made of glass, ceramic, metal plate, etc., which has a smaller coefficient of thermal expansion than the insulating resin 4. In the case of a metal plate, it is necessary to prevent short circuits. The thickness of the thin plate 8, whose surface is insulated according to the conditions, varies depending on the material, but is usually about 50 to 300 μm, which is a thickness that does not deform or break due to expansion and contraction of the insulating resin 4 due to temperature changes. Its size is approximately equal to the area of the insulating resin 4 that spreads around the opening 7 of the insulating plate 8.
以上のような構造にすると、半導体装置を温度変化の激
しｔ１環境で使用する場合や、特にそれを他の回路基板
にり７ｏ−等で半田付けする場合、絶縁性樹脂４の伸縮
によ勺応力を生ずるが、従来の構造であればＩＣチップ
１やポンディング部にその応力全部がかかっていたもの
を、薄板９とＩＣチップ１とで絶縁性樹脂４をはさみ込
むことによってこれを分散し、また薄板９を加圧するこ
とによって絶縁性樹脂４を充分に薄くすることが可能で
あるため、応力の絶対量を小さくすることができ、従っ
てチップ割れやポンディングオープンを防ぐことができ
る。更にＩＣチップ１の外側の絶縁性樹脂４の伸縮によ
る応力は、従来構造であれば導体リード３に全てかかり
断線しやすかったものが、これも薄板９に絶縁性樹脂４
が接着することによりその応力が抑制、緩和されてリー
ド断線を防ぐことが可能となる。With the above structure, when the semiconductor device is used in an environment with severe temperature changes t1, or especially when it is soldered to another circuit board with 7o-, etc., the expansion and contraction of the insulating resin 4 However, in the conventional structure, all of the stress would be applied to the IC chip 1 and the bonding part, but this is dispersed by sandwiching the insulating resin 4 between the thin plate 9 and the IC chip 1. Furthermore, since the insulating resin 4 can be made sufficiently thin by pressurizing the thin plate 9, the absolute amount of stress can be reduced, and chip cracking and pounding open can therefore be prevented. Furthermore, in the conventional structure, the stress due to the expansion and contraction of the insulating resin 4 on the outside of the IC chip 1 would be applied entirely to the conductor leads 3, which would easily cause wire breakage.
By adhering, the stress is suppressed and relaxed, making it possible to prevent lead breakage.
ｉ２図は本発明の別の実施例における半導体装置の断面
図である。ここで薄板１０は、その中央部に穴１１を設
け、ＩＣチップ１のポンディング部から絶縁性樹脂４の
外縁近傍までを覆う形状をしている。こうすることによ
り、特に強度的に弱いポンディング部と導体リード３に
加わる絶縁性樹脂４の応力を抑制して断線を防ぐ七共に
、絶縁性樹脂４が硬化する際に発生するガスを抜は易（
して樹脂内の気泡の発生を防ぎ、より信頼性の高い半導
体装置を提供することができる。尚この場合、薄板の形
伏としては第３図に示すように、薄板１２に小孔１３を
多数明けたものを用いても同様の効果が得られる。Figure i2 is a sectional view of a semiconductor device in another embodiment of the present invention. Here, the thin plate 10 has a hole 11 in its center and has a shape that covers from the bonding part of the IC chip 1 to the vicinity of the outer edge of the insulating resin 4. By doing this, the stress of the insulating resin 4 applied to the bonding part and the conductor lead 3, which is particularly weak in strength, is suppressed to prevent wire breakage, and the gas generated when the insulating resin 4 hardens is prevented. Easy (
By doing so, it is possible to prevent the generation of bubbles in the resin and provide a more reliable semiconductor device. In this case, the same effect can be obtained by using a thin plate 12 with a large number of small holes 13, as shown in FIG. 3, as the shape of the thin plate.
（発明の効果〕
以上述べたように本発明によれば、ＩＣチップをモール
ドする絶縁性樹脂の温度変化によ−る伸縮によって生ず
る応力を、その上に設けた薄板で抑制することにより、
チップ割れや、ポンディング部、導体リードの断線を防
ぐことができ、信頼性の高い半導体装置を得ることがで
きる。また薄板の厚みは加わるが、絶縁性樹脂の厚みは
薄（することができ、全体として薄く、厚みバラツキの
少ない半導体装置を得るととも可能である。尚、このモ
ールド構造は特に断線やチップ割れの生じやすい、チッ
プサイズの大きい半導体ＨＦＩに対して有効である。(Effects of the Invention) As described above, according to the present invention, the stress caused by the expansion and contraction due to temperature changes of the insulating resin used to mold the IC chip is suppressed by the thin plate provided thereon.
Chip cracking, bonding portions, and conductor lead breakage can be prevented, and a highly reliable semiconductor device can be obtained. In addition, although the thickness of the thin plate is added, the thickness of the insulating resin can be made thinner, making it possible to obtain a semiconductor device that is thinner overall and with less variation in thickness.In addition, this mold structure is particularly susceptible to wire breakage and chip cracking. This method is effective for semiconductor HFIs with large chip sizes that tend to cause problems.
第１図は本発明の半導体装置の実施例を示す断面図、第
２図は本発明の半導体装置の別の実施例を示す断面図、
第３図は本発明の半導体装置に用いる薄板の別の実施例
を示す平面図、！４図は従来の半導体８１７１を示す断
面図である。
１・・・ＩＣＣチップ ２・・・テープキャリア３・・
・導体リード ４・・・絶縁性樹脂５・・・能動面
６・・・側面
７・・・開口部 ８・・・絶縁板９．１０．１２
・・・薄板
１１・・・穴 １３・・・小孔以 上
出願人 セイコーエプソン株式会社
代理人 弁理士 最 上 務 他１名′、： ＼FIG. 1 is a sectional view showing an embodiment of the semiconductor device of the invention, FIG. 2 is a sectional view showing another embodiment of the semiconductor device of the invention,
FIG. 3 is a plan view showing another embodiment of the thin plate used in the semiconductor device of the present invention. FIG. 4 is a cross-sectional view showing a conventional semiconductor 8171. 1...ICC chip 2...Tape carrier 3...
・Conductor lead 4...Insulating resin 5...Active surface
6...Side surface 7...Opening part 8...Insulating plate 9.10.12
Thin plate 11... Hole 13... Small hole or more Applicant Seiko Epson Co., Ltd. Agent Patent attorney Tsutomu Mogami and 1 other person',: \
Claims (2)
ードにインナーリードボンディングされる半導体素子の
少なくとも能動面および前記開口部周囲の前記絶縁板が
絶縁性樹脂によりモールドされてなる半導体装置におい
て、前記開口部より大きい外形をなし、かつ前記絶縁性
樹脂よりも低い熱膨張率を有する材質の薄板を、前記半
導体素子の能動面側に前記絶縁性樹脂をはさみ込むよう
な形で設けたことを特徴とする半導体装置。(1) In a semiconductor device in which at least the active surface of a semiconductor element that is inner lead bonded to a conductor lead protruding into an opening of an insulating plate made of resin or the like and the insulating plate around the opening are molded with an insulating resin. , a thin plate made of a material having a larger outer diameter than the opening and having a coefficient of thermal expansion lower than that of the insulating resin is provided on the active surface side of the semiconductor element so as to sandwich the insulating resin. A semiconductor device characterized by:
ング部から前記絶縁性樹脂の外縁近傍を覆うことを特徴
とする特許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the thin plate covers at least the vicinity of the outer edge of the insulating resin from the bonding portion of the semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13836687A JPS63302542A (en) | 1987-06-02 | 1987-06-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13836687A JPS63302542A (en) | 1987-06-02 | 1987-06-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63302542A true JPS63302542A (en) | 1988-12-09 |
Family
ID=15220250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13836687A Pending JPS63302542A (en) | 1987-06-02 | 1987-06-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63302542A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5173764A (en) * | 1991-04-08 | 1992-12-22 | Motorola, Inc. | Semiconductor device having a particular lid means and encapsulant to reduce die stress |
-
1987
- 1987-06-02 JP JP13836687A patent/JPS63302542A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5173764A (en) * | 1991-04-08 | 1992-12-22 | Motorola, Inc. | Semiconductor device having a particular lid means and encapsulant to reduce die stress |
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