JP2630299B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2630299B2 JP2630299B2 JP7072925A JP7292595A JP2630299B2 JP 2630299 B2 JP2630299 B2 JP 2630299B2 JP 7072925 A JP7072925 A JP 7072925A JP 7292595 A JP7292595 A JP 7292595A JP 2630299 B2 JP2630299 B2 JP 2630299B2
- Authority
- JP
- Japan
- Prior art keywords
- island
- semiconductor device
- small
- semiconductor element
- corner
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
銅系合金のリードフレームを使用した薄型の樹脂封止型
半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a thin resin-encapsulated semiconductor device using a copper alloy lead frame.
【０００２】[0002]
【従来の技術】高速化に伴う高消費電力化および高発熱
化の傾向に対応して、半導体素子は放熱性の向上が要求
されている。そのため、樹脂封止型半導体装置のリード
フレームには、素材として熱伝導率の高い銅系合金を広
く採用するようになってきている。しかしながら、半導
体素子の構成材料であるシリコンと銅係合金とは熱膨張
係数が約１０倍程度の差異があるため、外部環境温度の
上昇、下降によってバイメタル効果が生じ、封止樹脂に
繰返し応力が負荷される。特に半導体装置の封止樹脂厚
が薄い場合、バイメタル効果による応力のため樹脂にク
ラックが生じ、このクラックが外部に達することにより
半導体装置の信頼性が損われる。2. Description of the Related Art In response to the trend of higher power consumption and higher heat generation accompanying higher speeds, semiconductor elements are required to have improved heat dissipation. Therefore, a copper-based alloy having high thermal conductivity has been widely used as a material for a lead frame of a resin-encapsulated semiconductor device. However, since there is a difference in thermal expansion coefficient of about 10 times between silicon, which is a constituent material of the semiconductor element, and copper engagement gold, a bimetal effect occurs due to an increase or decrease in the external environment temperature, and a repeated stress is applied to the sealing resin. Loaded. In particular, when the thickness of the sealing resin of the semiconductor device is small, cracks occur in the resin due to the stress due to the bimetal effect, and the cracks reach the outside, thereby impairing the reliability of the semiconductor device.
【０００３】このような問題点に対処するため、従来、
この種の半導体装置のリードフレームのアイランドには
上記応力分散のための複数のスリットを設けることによ
り、上記アイランドを分割していた。In order to address such problems, conventionally,
A plurality of slits for dispersing the stress are provided on an island of a lead frame of this type of semiconductor device, thereby dividing the island.
【０００４】従来の半導体装置を部分破断平面図及び半
導体素子搭載後のＡＡ断面図で示す図４（Ａ），（Ｂ）
を参照すると、この従来の半導体装置は、半導体素子４
を搭載しスリット３により分割された９つの小アイラン
ド７から成るアイランド１と、コーナ部の小アイランド
の外側コーナに接合されアイランド１をリードフレーム
の外枠（図示省略）に支持する吊ピン２と、アイランド
１に設けた複数のスリット３とを含むリードフレーム６
と、半導体素子４と、半導体素子４をアイランド１に固
着するろう材等のマウント材５とを備える。FIGS. 4A and 4B show a conventional semiconductor device in a partially broken plan view and an AA sectional view after mounting a semiconductor element.
, This conventional semiconductor device has a semiconductor element 4
And an island 1 composed of nine small islands 7 divided by slits 3 and a suspending pin 2 joined to the outer corner of the small island at the corner to support the island 1 on the outer frame (not shown) of the lead frame. Frame 6 including a plurality of slits 3 provided in island 1
And a mounting element 5 such as a brazing material for fixing the semiconductor element 4 to the island 1.
【０００５】次に、図４を参照して、従来の半導体装置
のクラック防止動作について説明すると、アイランド１
はスリット３で９つの小アイランド７に分割されている
ので半導体素子４とアイランド１とのバイメタル効果が
抑制され、温度サイクル時の樹脂クラックの発生が防止
できる。Next, the operation of the conventional semiconductor device for preventing cracks will be described with reference to FIG.
Is divided into nine small islands 7 by the slits 3, the bimetal effect between the semiconductor element 4 and the islands 1 is suppressed, and the occurrence of resin cracks during a temperature cycle can be prevented.
【０００６】しかし、半導体素子４をアイランド１に搭
載するためのマウント材５の加熱硬化工程中において、
上記バイメタル効果のため、アイランド１が上下方向に
変位する。スリット３の存在によりこの変位は増幅され
る。このような状態で樹脂封止を行うと、封止樹脂から
の半導体素子４表面やアイランド１裏面の露出が生じ、
これらは不良品として廃棄せざるを得ない。However, during the heating and curing step of the mounting material 5 for mounting the semiconductor element 4 on the island 1,
Due to the bimetal effect, the island 1 is vertically displaced. This displacement is amplified by the presence of the slit 3. When resin sealing is performed in such a state, the surface of the semiconductor element 4 and the back surface of the island 1 are exposed from the sealing resin,
These must be discarded as defective products.
【０００７】この変位は、アイランド１のサイズに比例
して大きくなる性質がある。例えば、アイランド１のサ
イズが１５．０ｍｍ角を越えると上記変位は４００μｍ
を越え、これを樹脂封止すると半導体素子４の上側とア
イランド１の下側の樹脂流路厚の違いから曲げモーメン
トが働き、半導体素子４の表面もしくはアイランド１の
裏面が封止樹脂の外部に露出し、封入工程の歩留が著し
く低下する。This displacement tends to increase in proportion to the size of the island 1. For example, when the size of the island 1 exceeds 15.0 mm square, the displacement is 400 μm.
When the resin is sealed, a bending moment acts due to the difference in the thickness of the resin flow path between the upper side of the semiconductor element 4 and the lower side of the island 1, so that the surface of the semiconductor element 4 or the back side of the island 1 is outside the sealing resin. And the yield of the encapsulation process is significantly reduced.
【０００８】[0008]
【発明が解決しようとする課題】上述した従来の半導体
装置は、マウント材の加熱硬化工程中、半導体素子とア
イランドとの熱膨張差によるバイメタル効果のためアイ
ランドの上下方向変位が生じ、またスリットの存在によ
りこの変位が増幅されるので、このまま樹脂封止を行う
と半導体素子表面やアイランド裏面の露出が生じ、著し
い歩留りの低下要因となるという欠点があった。In the above-described conventional semiconductor device, the island is displaced in the vertical direction due to a bimetal effect due to a difference in thermal expansion between the semiconductor element and the island during the heating and curing step of the mount material. Since this displacement is amplified by the presence of the resin, if the resin is sealed as it is, the surface of the semiconductor element and the back surface of the island are exposed, which has a drawback that the yield is significantly reduced.
【０００９】[0009]
【課題を解決するための手段】本発明の半導体装置は、
スリットにより複数の小アイランドに分割した半導体素
子の載置用のアイランドと、前記アイランドの支持用の
複数の吊ピンとを含むリードフレームとを備え、前記ア
イランドがほぼ中央部近傍に前記吊ピンとの接合部を備
える樹脂封止型の半導体装置において、前記アイランド
が、前記中央部の小アイランドの外側コーナに前記接合
部を備え、 前記コーナ部の前記小アイランド外側コーナ
に接合し前記吊ピンの両側に平行に設けた第１，第２の
サブ吊ピンと、 前記アイランドの外側に設けられ前記第
１，第２のサブ吊ピンの各々を固定する絶縁材料のフィ
ルム状部材とを備えて構成されている。According to the present invention, there is provided a semiconductor device comprising:
And the island of置用mounting of the semiconductor device divided into a plurality of small islands by a slit, and a lead frame including a plurality of extending portions for supporting the island, the A
Iland has a joint with the hanging pin near the center.
In the semiconductor device of a resin sealed type Ru example, the island, the bonding to the outer corners of the small islands of the central portion
A small island outside corner of the corner portion
1 and 2 provided in parallel on both sides of the hanging pin
A sub-suspension pin, and the
1, a filter of insulating material for fixing each of the second sub-suspension pins.
And a lumped member .
【００１０】[0010]
【実施例】次に、本発明の第１の実施例を図４と共通の
構成要素には共通の参照文字／数字を付して同様に部分
破断平面図及び半導体素子搭載後のＡＡ断面図で示す図
１（Ａ），（Ｂ）を参照すると、この図に示す本実施例
の半導体装置は、従来と共通のスリット３と半導体素子
４とマウント材５とに加えて、アイランド１の代りにス
リット３により分割された５つの小アイランド７と４つ
のコーナ小アイランド８を含むアイランド１Ａと、吊ピ
ン２の代りにコーナ小アイランド８に設けたコーナスリ
ット１０を介して内側コーナに設けた吊ピン接合部９に
接合した吊ピン２Ａとを含むリードフレーム６Ａを備え
る。Next, a first embodiment of the present invention will be described with reference to FIG. 4 in which components common to those in FIG. Referring to FIGS. 1A and 1B, the semiconductor device of the present embodiment shown in FIG. 1 includes a slit 3, a semiconductor element 4, and a mounting material 5 which are common to the related art, An island 1A including five small islands 7 and four corner small islands 8 divided by slits 3 and a suspension provided at an inner corner through a corner slit 10 provided in the corner small island 8 instead of the suspension pin 2. A lead frame (6A) including a suspension pin (2A) joined to the pin joint (9) is provided.
【００１１】次に、図１を参照して本実施例の作用につ
いて説明すると、アイランド１Ａのマウント材５の塗布
領域は、吊ピン２Ａが接合するコーナ小アイランド８を
除く５つの小アイランド７の全面と、コーナ部小アイラ
ンド８の吊ピン接合部９に接合された吊ピン２Ａを除く
部分である。このような構造の場合、半導体素子４のサ
イズが１５ｍｍ角以上になっても吊ピン２はあたかも半
導体素子４のサイズが５ｍｍ角程度のアイランドに接合
していることと等価となるため、マウント材５を加熱硬
化させてもアイランドの上下方向の変位は０〜５０μｍ
程度に抑えられる。Next, the operation of the present embodiment will be described with reference to FIG. 1. The application area of the mounting material 5 of the island 1A is the same as that of the five small islands 7 except the corner small island 8 to which the hanging pin 2A is joined. It is a portion excluding the extending portions 2A joined to the extending portions 9 of the corner portion small islands 8 on the entire surface. In the case of such a structure, even if the size of the semiconductor element 4 becomes 15 mm square or more, the extending portion 2 is equivalent to joining the semiconductor element 4 to an island having a size of about 5 mm square. 5 even when cured by heating, the vertical displacement of the island is 0 to 50 μm.
It can be suppressed to the extent.
【００１２】しかもアイランド１Ａは分割されているた
め、５００サイクル以上の温度サイクル試験（−６０℃
〜＋１５０℃程度）の実施結果においてもパッケージク
ラックの発生はなく、半導体装置の信頼性も高いという
結果が得られている。In addition, since the island 1A is divided, a temperature cycle test of 500 cycles or more (−60 ° C.)
(About + 150 ° C.), there is no package crack, and the semiconductor device has high reliability.
【００１３】本発明の第２の実施例を図１と共通の構成
要素には共通の参照文字／数字を付して同様に部分破断
平面図及び半導体素子搭載後のＡＡ断面図で示す図２
（Ａ），（Ｂ）を参照すると、この図に示す本実施例の
半導体装置の第１の実施例との相違点は、アイランド１
Ｂが吊ピン２Ｂの接合用の吊ピン接合部９Ａを備える中
央部のセンタ小アイランド１１を含み、吊ピン２Ｂがこ
のセンタ小アイランド１１に直接接合する構造をもつリ
ードフレーム６Ｂを備えることである。FIG. 2 shows a second embodiment of the present invention in the same manner as in FIG. 1 with common reference characters / numerals attached thereto and similarly in a partially cutaway plan view and an AA sectional view after mounting a semiconductor element.
Referring to FIGS. 7A and 7B, the difference between the semiconductor device of the present embodiment and the first embodiment shown in FIG.
B includes a center small island 11 having a center portion provided with a hanging pin joining portion 9A for joining the hanging pin 2B, and the extending portion 2B includes a lead frame 6B having a structure directly joined to the center small island 11. .
【００１４】この結果、マウント材５の加熱硬化による
アイランドの上下方向変位はさらに小さく低減できる。As a result, the vertical displacement of the island due to the heat curing of the mount member 5 can be further reduced.
【００１５】本発明の第３の実施例を図２と共通の構成
要素には共通の参照文字／数字を付して同様に部分破断
平面図及び半導体素子搭載後のＡＡ断面図で示す図３
（Ａ），（Ｂ）を参照すると、この図に示す本実施例の
半導体装置の第２の実施例との相違点は、コーナ小アイ
ランド８Ａが吊ピン２Ｂと平行に導出されたサブ吊ピン
１３と、アイランド１Ｃの外部に設けたサブ吊ピン１３
の固定用の絶縁フィルム１２とを含むリードフレーム６
Ｂを備えることである。FIG. 3 shows a third embodiment of the present invention in the same manner as in FIG. 2 with common reference characters / numerals added thereto and similarly in a partially broken plan view and an AA sectional view after mounting the semiconductor element.
Referring to (A) and (B), the difference between the semiconductor device of the present embodiment and the second embodiment shown in this figure is that the corner small island 8A is extended in parallel with the suspension pin 2B. 13 and a sub suspension pin 13 provided outside the island 1C.
Lead frame 6 including insulating film 12 for fixing
B.
【００１６】本実施例では、センター小アイランド１１
以外の小アイランド７，８Ａは半導体素子４と固着して
いないため、より一層の上下方向変位の低減と温度サイ
クルによる耐クラック性が向上し、半導体装置の信頼性
が向上する。In this embodiment, the center small island 11
Since the other small islands 7 and 8A are not fixed to the semiconductor element 4, the vertical displacement is further reduced, crack resistance due to a temperature cycle is improved, and the reliability of the semiconductor device is improved.
【００１７】[0017]
【発明の効果】以上説明したように、本発明の半導体装
置は、アイランドのほぼ中央部近傍に前記吊ピンとの接
合部を備えることにより、マウント材の加熱硬化工程中
の半導体素子とアイランドとの熱膨張差によるバイメタ
ル効果のためのアイランドの上下方向変位が抑圧される
ので歩留り低下の要因を除去できるという効果がある。As described above, the semiconductor device of the present invention is provided with a joint portion with the extending portion near the center of the island, so that the semiconductor element and the island can be connected to each other during the step of heating and curing the mounting material. Since the vertical displacement of the island due to the bimetal effect due to the difference in thermal expansion is suppressed, there is an effect that the factor of the yield reduction can be eliminated.
【図１】本発明の半導体装置の第１の実施例を示す部分
破断平面図及びそのＡＡ断面図である。FIG. 1 is a partially broken plan view showing a first embodiment of a semiconductor device according to the present invention, and an AA sectional view thereof.
【図２】本発明の半導体装置の第２の実施例を示す部分
破断平面図及びそのＡＡ断面図である。FIG. 2 is a partially cutaway plan view showing a second embodiment of the semiconductor device of the present invention, and an AA sectional view thereof.
【図３】本発明の半導体装置の第３の実施例を示す部分
破断平面図及びそのＡＡ断面図である。FIG. 3 is a partially broken plan view showing a third embodiment of the semiconductor device of the present invention, and an AA sectional view thereof.
【図４】従来の半導体装置の一例を示す部分破断平面図
及びそのＡＡ断面図である。FIG. 4 is a partially cutaway plan view showing an example of a conventional semiconductor device and an AA sectional view thereof.
１，１Ａ，１Ｂ，１Ｃ アイランド ２，２Ａ，２Ｂ 吊ピン ３ スリット ４ 半導体素子 ５ マウント材 ６，６Ａ，６Ｂ，６Ｃ リードフレーム ７ 小アイランド ８，８Ａ コーナ小アイランド ９，９Ａ 吊ピン接合部 １０ コーナースリット １１ センタ小アイランド １２ 絶縁フィルム １３ サブ吊ピン 1, 1A, 1B, 1C Island 2, 2A, 2B Hanging pin 3 Slit 4 Semiconductor element 5 Mounting material 6, 6A, 6B, 6C Lead frame 7 Small island 8, 8A Corner small island 9, 9A Hanging pin joint 10 Corner Slit 11 Center small island 12 Insulating film 13 Sub hanging pin
Claims (1)
割した半導体素子の載置用のアイランドと、前記アイラ
ンドの支持用の複数の吊ピンとを含むリードフレームと
を備え、前記アイランドがほぼ中央部近傍に前記吊ピン
との接合部を備える樹脂封止型の半導体装置において、 前記アイランドが、前記中央部の小アイランドの外側コ
ーナに前記接合部を備え、 前記コーナ部の前記小アイランド外側コーナに接合し前
記吊ピンの両側に平行に設けた第１，第２のサブ吊ピン
と、 前記アイランドの外側に設けられ前記第１，第２のサブ
吊ピンの各々を固定する絶縁材料のフィルム状部材と を
備えることを特徴とする半導体装置。1. A slit is divided into a plurality of small islands.
An island for mounting the split semiconductor element,
A lead frame including a plurality of hanging pins for supporting the
Equipped, The island is located near the center of the hanging pin.
With a jointWherein the island is,SaidOutside the small island in the center
To the joint, Before joining to the small island outside corner of the corner part
First and second sub-suspension pins provided in parallel on both sides of the suspension pin
When, The first and second sub-circuits provided outside the island
A film-like member made of an insulating material for fixing each of the hanging pins; To
A semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7072925A JP2630299B2 (en) | 1995-03-30 | 1995-03-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7072925A JP2630299B2 (en) | 1995-03-30 | 1995-03-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08274244A JPH08274244A (en) | 1996-10-18 |
| JP2630299B2 true JP2630299B2 (en) | 1997-07-16 |
Family
ID=13503427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7072925A Expired - Lifetime JP2630299B2 (en) | 1995-03-30 | 1995-03-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2630299B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3034814B2 (en) * | 1997-02-27 | 2000-04-17 | 沖電気工業株式会社 | Lead frame structure and method of manufacturing semiconductor device |
| JP4738250B2 (en) * | 2006-05-19 | 2011-08-03 | パナソニック株式会社 | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04186666A (en) * | 1990-11-19 | 1992-07-03 | Oki Electric Ind Co Ltd | Lead frame of semiconductor device sealed with resin |
| JPH05235244A (en) * | 1992-02-26 | 1993-09-10 | Hitachi Ltd | Lead frame and semiconductor device using the same |
| JPH05326812A (en) * | 1992-05-27 | 1993-12-10 | Sony Corp | Lead frame for semiconductor device, wire bonding device and wire bonding method for semiconductor chip using thereof |
-
1995
- 1995-03-30 JP JP7072925A patent/JP2630299B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08274244A (en) | 1996-10-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970304 |