JPS58182237A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS58182237A
JPS58182237A JP57065210A JP6521082A JPS58182237A JP S58182237 A JPS58182237 A JP S58182237A JP 57065210 A JP57065210 A JP 57065210A JP 6521082 A JP6521082 A JP 6521082A JP S58182237 A JPS58182237 A JP S58182237A
Authority
JP
Japan
Prior art keywords
circuit
test
pad
integrated circuit
test circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57065210A
Other languages
Japanese (ja)
Inventor
Kazuharu Takeda
武田　和春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57065210A priority Critical patent/JPS58182237A/en
Publication of JPS58182237A publication Critical patent/JPS58182237A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To realize reduction in size through common use of pads for internal circuit and IC test circuit. CONSTITUTION:Terminals of test circuit 1 are connected to a pad 2 for internal circuit and a pad 3 for test circuit. An internal circuit 4 is connected to the pad 2 for signal input/output or power supply ON/OFF. At this time, the test pad 3 is opened and it does not give any influence on the test circuit 1. According to this structure, area for pad is drastically reduced and IC can be reduced in size.

Description

【発明の詳細な説明】 本発明は、集積回路を構成する内部回路のパッドと集積
回路の試験回路のパッドと全兼用できるようにし、両パ
ッドの共用化を図った半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit that can be used both as a pad for an internal circuit constituting an integrated circuit and as a pad for a test circuit of the integrated circuit.

従来、半導体集積回路の中には、プロセス及び回路動作
の評価を行なうための試験回路が予め組み込まれている
。試験回路としては、例えばトランジスタ、ダイオード
、コンデンサ、抵抗等があり、集積回路を製造した後前
述の試験回路にょって測定し、所期の特性が得られ次か
どうかを判定してプロセス及び回路動作の評価を行なえ
るようＫなっている。2. Description of the Related Art Conventionally, a test circuit for evaluating process and circuit operation is pre-installed in a semiconductor integrated circuit. Test circuits include, for example, transistors, diodes, capacitors, resistors, etc. After the integrated circuit is manufactured, it is measured using the test circuit described above to determine whether the desired characteristics are obtained and the process and circuit are tested. It is set to K so that the operation can be evaluated.

しかし、試験回路ＫＦｉ、試験回路とその素子の人出力
の几めの試験回路用のテストパッドを必要とし、このテ
ストパッドは試験回路の端子数だけ必要であった。また
、テストパッドは測定の都度探針ｔＷＩ触させる必要が
あり、その面構をある程度大きくしなければならなかっ
た。そのため、集積回路に試験回路を内蔵させると、テ
ストパッドの分だけ集積回路の有効面接が減少し、延い
ては集積回路の小型化促進の障害となってい次。However, test pads for the test circuit KFi, test circuits, and the human outputs of the test circuits and their elements are required, and the number of test pads is equal to the number of terminals of the test circuit. In addition, it was necessary to touch the test pad with the probe tip tWI every time a measurement was made, and the surface structure of the test pad had to be made large to some extent. Therefore, when a test circuit is built into an integrated circuit, the effective surface area of the integrated circuit is reduced by the amount of the test pad, which in turn becomes an obstacle to the miniaturization of integrated circuits.

本発明は上記の欠点に＆みてなされたもので、集積回路
に内蔵された試験回路を導出するためのテストパッドと
、集積回路の内部回路を外部端子擲に導出するための内
部回路用のパッドを共用化することにより、集積回路の
ｒｋＪ槽を減少して小型化を図るとと−に、試験回路の
測定を容易にした半導体集積回路の提供を目的とする。The present invention has been made in view of the above drawbacks, and includes a test pad for deriving a test circuit built into an integrated circuit, and an internal circuit pad for deriving the internal circuit of the integrated circuit to an external terminal. It is an object of the present invention to provide a semiconductor integrated circuit in which the rkJ tank of the integrated circuit is reduced and the size thereof is reduced by sharing the rkJ tank, and the measurement of the test circuit is facilitated.

以下、図面に示す実施例に基づいて本発＠會説明する。The present invention will be explained below based on the embodiment shown in the drawings.

図［１ｉにおいて、ｌＦｉ試験回路、２は内部回路用の
パッド、３は試験回路用のテストパッド、　４ｔｌ；を
内部回路、５はこれらのものを内蔵している集積回路で
ある。試験回路１は２つの端子が内部回路用のパッド２
と試験回路用のテストパッド３にそｈぞれ接続されてい
る。このようＫｌｉ続された試験回路１を備えた集積回
路５０通常の動作は、パッド２にワイヤボンディング等
し、これによ）内部回路４０入出力あるｈは電源の導出
入１行なう。In FIG. 1i, the lFi test circuit, 2 is a pad for an internal circuit, 3 is a test pad for a test circuit, 4tl is an internal circuit, and 5 is an integrated circuit containing these things. Test circuit 1 has two terminals as pad 2 for internal circuit.
and a test pad 3 for the test circuit. In the normal operation of the integrated circuit 50 equipped with the test circuit 1 connected in this way, the pad 2 is wire-bonded, etc., so that the input/output h of the internal circuit 40 is connected to the input/output of the power supply.

この場合、テストパッド３Ｆｉ開放されているので試験
回路ＩＫはなんの影響も与えない。In this case, since the test pad 3Fi is open, the test circuit IK has no effect.

一方、試験回路１ｔｌｌＪ定するときは、パッド２に既
にワイヤボンディングしてｗ！絖されている集積回路の
ピン（ワイヤ）と、テストパッド３に立て良計を便用し
て試験回路ｌの入出力尋を行なう。On the other hand, when setting up the test circuit 1tllJ, wire bonding has already been done to pad 2! Input/output tests of the test circuit 1 are carried out using the pins (wires) of the integrated circuit being wired and a suitable meter on the test pad 3.

この場合も、内部回路は動作しないので試験回路に影響
を与えることがない。また、テストノ（ラド３に針を立
てればよいので測定が非常に行ないやすい。In this case as well, the internal circuit does not operate, so the test circuit is not affected. In addition, measurement is very easy as all you have to do is put the needle on the test tube (RAD 3).

図示した実施例では２端子の試験回路について説明した
が、３端子以上の試験回路でも、本実施例と同様に試験
回路用のテストノ（ラドを内部回路用のパッドと共用化
することができる。In the illustrated embodiment, a two-terminal test circuit has been described, but even in a test circuit with three or more terminals, the test pad for the test circuit can be shared with the pad for the internal circuit as in this embodiment.

以上の如く本発明によれば、試験回路用のテストパッド
と内部回路用のパッドを兼用して使用し、その共用化を
図ることができるので、従来必要とされてい九バンドの
ための面積を大幅に削減でき集積回路を小型化すること
がで逃る。これにより、歩留りが向上し、装置轡への実
装密度を高めることができる。さらに、テストパッドに
のみ針を立てればよいので測定が非常に容易になる。As described above, according to the present invention, it is possible to use the test pad for the test circuit and the pad for the internal circuit, and to share the space. This can be significantly reduced by miniaturizing integrated circuits. As a result, the yield can be improved and the packaging density on the device can be increased. Furthermore, since it is only necessary to set the needle on the test pad, measurement becomes very easy.

【図面の簡単な説明】[Brief explanation of the drawing]

図６ｊＪＦｉ本発明学導体集檀回路の一実施例を示す。 １・・・試験回路　　　２・・・（内部回路用の）パッ
ド３・・・（試験回路用の）テストパッド４・・・内部
回路　　　　　５・・・集積回路出願人　　日本電気株
式会社FIG. 6j shows an embodiment of the JFi inventive conductor assembly circuit. 1... Test circuit 2... Pad (for internal circuit) 3... Test pad (for test circuit) 4... Internal circuit 5... Integrated circuit applicant NEC Corporation

Claims (1)

【特許請求の範囲】[Claims] 集積回路に内蔵されている試験回路を導出するためのパ
ッドと、前記集積回路の内部回路を導出し外部端千尋と
の接続を行なうためのバンドとを共用化したことを特徴
とする半導体集積回路。A semiconductor integrated circuit characterized in that a pad for deriving a test circuit built into the integrated circuit and a band for deriving the internal circuit of the integrated circuit and connecting it to an external end are shared. .
JP57065210A 1982-04-19 1982-04-19 Semiconductor integrated circuit Pending JPS58182237A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57065210A JPS58182237A (en) 1982-04-19 1982-04-19 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57065210A JPS58182237A (en) 1982-04-19 1982-04-19 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS58182237A true JPS58182237A (en) 1983-10-25

Family

ID=13280318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57065210A Pending JPS58182237A (en) 1982-04-19 1982-04-19 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS58182237A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5466956A (en) * 1993-11-18 1995-11-14 Nec Corporation Semiconductor integrated circuit device with electrode for measuring interlayer insulator capacitance
US6037795A (en) * 1997-09-26 2000-03-14 International Business Machines Corporation Multiple device test layout
US6184569B1 (en) * 1998-01-13 2001-02-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor chip inspection structures
US7307441B2 (en) 2002-05-15 2007-12-11 Samsung Electronics Co., Ltd. Integrated circuit chips and wafers including on-chip test element group circuits, and methods of fabricating and testing same
US8890556B2 (en) 2011-10-26 2014-11-18 International Business Machines Corporation Real-time on-chip EM performance monitoring
US8917104B2 (en) 2011-08-31 2014-12-23 International Business Machines Corporation Analyzing EM performance during IC manufacturing

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5466956A (en) * 1993-11-18 1995-11-14 Nec Corporation Semiconductor integrated circuit device with electrode for measuring interlayer insulator capacitance
US6037795A (en) * 1997-09-26 2000-03-14 International Business Machines Corporation Multiple device test layout
US6184569B1 (en) * 1998-01-13 2001-02-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor chip inspection structures
DE19836614C2 (en) * 1998-01-13 2003-08-21 Mitsubishi Electric Corp Semiconductor chip with line on a corner part of the semiconductor chip
US7307441B2 (en) 2002-05-15 2007-12-11 Samsung Electronics Co., Ltd. Integrated circuit chips and wafers including on-chip test element group circuits, and methods of fabricating and testing same
US8917104B2 (en) 2011-08-31 2014-12-23 International Business Machines Corporation Analyzing EM performance during IC manufacturing
US8890556B2 (en) 2011-10-26 2014-11-18 International Business Machines Corporation Real-time on-chip EM performance monitoring

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