JPS58171796A - 並列二重化記憶装置 - Google Patents
並列二重化記憶装置Info
- Publication number
- JPS58171796A JPS58171796A JP57054857A JP5485782A JPS58171796A JP S58171796 A JPS58171796 A JP S58171796A JP 57054857 A JP57054857 A JP 57054857A JP 5485782 A JP5485782 A JP 5485782A JP S58171796 A JPS58171796 A JP S58171796A
- Authority
- JP
- Japan
- Prior art keywords
- storage device
- time width
- circuit
- parallel
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000872 buffer Substances 0.000 claims description 10
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 7
- 230000009977 dual effect Effects 0.000 abstract description 4
- 230000005764 inhibitory process Effects 0.000 abstract 2
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 12
- 230000015654 memory Effects 0.000 description 8
- 230000004913 activation Effects 0.000 description 4
- 241000269821 Scombridae Species 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 235000020640 mackerel Nutrition 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 1
- 101100460719 Mus musculus Noto gene Proteins 0.000 description 1
- 235000019013 Viburnum opulus Nutrition 0.000 description 1
- 244000071378 Viburnum opulus Species 0.000 description 1
- 101100187345 Xenopus laevis noto gene Proteins 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 210000000554 iris Anatomy 0.000 description 1
- 239000000454 talc Substances 0.000 description 1
- 229910052623 talc Inorganic materials 0.000 description 1
- 210000001215 vagina Anatomy 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57054857A JPS58171796A (ja) | 1982-04-02 | 1982-04-02 | 並列二重化記憶装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57054857A JPS58171796A (ja) | 1982-04-02 | 1982-04-02 | 並列二重化記憶装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58171796A true JPS58171796A (ja) | 1983-10-08 |
| JPH041375B2 JPH041375B2 (enExample) | 1992-01-10 |
Family
ID=12982256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57054857A Granted JPS58171796A (ja) | 1982-04-02 | 1982-04-02 | 並列二重化記憶装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58171796A (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH076099A (ja) * | 1992-12-17 | 1995-01-10 | Internatl Business Mach Corp <Ibm> | リモート・データの2重化のためのシステム及び方法 |
-
1982
- 1982-04-02 JP JP57054857A patent/JPS58171796A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH076099A (ja) * | 1992-12-17 | 1995-01-10 | Internatl Business Mach Corp <Ibm> | リモート・データの2重化のためのシステム及び方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH041375B2 (enExample) | 1992-01-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2572292B2 (ja) | 非同期データ伝送装置 | |
| JPH0581143A (ja) | メモリアレイのアドレスと中味とをチエツクする装置及び方法 | |
| JPH02154177A (ja) | 複数個の異なった機能ブロックを有する単一のチップにテストを行なうためのモジュールのテスト構造 | |
| JPS59142799A (ja) | バツクアツプ用蓄電装置付二重化記憶装置 | |
| JP2001167005A (ja) | メモリ診断方法とメモリ診断回路および半導体記憶装置 | |
| JPS6249676B2 (enExample) | ||
| US4918650A (en) | Memory control interface apparatus | |
| JPS58171796A (ja) | 並列二重化記憶装置 | |
| JP3872922B2 (ja) | 半導体記憶装置及びメモリ混載ロジックlsi | |
| JPS6129024B2 (enExample) | ||
| JP3165598B2 (ja) | 先入先出メモリのバスインタフェース装置 | |
| JPH0238969B2 (enExample) | ||
| JPS6349809B2 (enExample) | ||
| GB2084768A (en) | Circuit arrangement for rapidly exchanging data between the memory of an electronic processor and the interface units of its peripheral units | |
| JPS5829195A (ja) | 半導体メモリ | |
| US4470128A (en) | Control arrangement for magnetic bubble memories | |
| SU1070608A1 (ru) | Резервированное запоминающее устройство | |
| SU1256034A1 (ru) | Устройство дл сопр жени двух ЭВМ с общей пам тью | |
| SU1310835A1 (ru) | Устройство дл сопр жени двух вычислительных машин | |
| JPS61161560A (ja) | メモリ装置 | |
| JPS6321276B2 (enExample) | ||
| SU1075312A1 (ru) | Запоминающее устройство с коррекцией ошибок | |
| JPH06208539A (ja) | 高速データ転送方式 | |
| SU849299A1 (ru) | Запоминающее устройство | |
| JPH03100751A (ja) | 入出力処理装置 |