JPS58171796A - Storage device of parallel duplex structure - Google Patents

Abstract

PURPOSE:To improve the reliability, by inhibiting periodically be access request to a parallel dual storage device and setting two kinds of inhibition time width and performing only the refresh in the first time width and performing the refresh and the access request in the second time width. CONSTITUTION:The access request from a CPU to a parallel dual storage device 10 is inhibited periodically, and two kinds of inhibition time width are set. When the first time width is set, the refresh request is transmitted to one of two storage devices 1 and 2 within the first time width. When the second time width is set, contents of the first storage device are read out and contents of the second storage device are refreshed in the first half of the second time width, and the write request is transmitted to the second storage device and contents of the first storage device are refreshed in the latter half. Thus, contents of two storage devices are made coincident with each other without stopping normal operations to restart the parallel dual operation easily when a fault is recovered.

Description

[Detailed description of the invention] The present invention relates to a parallel duplex storage device for an information processing device.

Reliability O1j' in combinator system
It is known that various techniques have been adopted to create systems with high IIJ degrees. Among them, the main memory (MEM) Fi is shared by multiple central processing units (CPUs) and p1 main 5ati
If there is a failure in the device, the system will go down, so in order to achieve high reliability, a method of multiplexing 1*column of the main memory has been proposed for a long time. In the parallel duplex system, the main memory devices are connected in parallel to increase the reliability of the entire system. Therefore, it goes without saying that if one of the duplexed main storage devices suffers a failure, it is desirable to cause the failure, recover the Nine Seals from the failure as quickly as possible, and continue parallel operation. . However, with the conventional main memory O parallel duplication technology, if a failure occurs and the device is recovered from the failure, the two duplexed main memories
It is relatively important to match the storage contents of e. Therefore, in conventional duplex main storage devices, this point has not been considered at all, or even if it has been considered, a lot of hardware has been added to match the above-mentioned memory contents and the number of points per main storage device has been increased. ) will reduce the reliability of the system.

After all, this usually greatly reduces the effect of increasing the number of elfs by parallel duplexing. Another disadvantage of the conventional technology is that it is not possible to match the stored contents of the two main storage devices without temporarily stopping the normal operation of the computer.

An object of the present invention is to match the contents of two parallel duplexed main storage devices with almost no effect on normal operation of the system when recovering from a failure, so that parallel duplex operation can be easily restarted. Thus, it is possible to provide a parallel duplex storage device configured by adding a small amount of hardware.

In the present invention, access requests from the central processing unit to the parallel duplex storage device are periodically prohibited. 9. This prohibited time width can be set to the first time width and the third time width, and when the first time width is set, the IRT parallel duplex storage device A refresher request is sent to one or both of the two storage devices making up the storage device within a first time interval. on the other hand,
When the second time width is set, the contents of the WJl storage device of the snowball storage devices are extracted and the contents of the third storage device are refreshed in the first half of the second time width. In the second half of the second time span, the contents of the first storage device t IJ
7, and sends a write request attached to the second storage device. As write data when this write request is issued, data that can be read from the first storage device in the first half of the first half of the time period is used. Furthermore, the destination addresses of the same operation requests to be sent in the second time range are fixed to the same address value for both storage devices, and then the series of operation requests t-parameters are fixed to the same address value. All addresses KtJ of the redundant storage device are sent.

Hereinafter, the parallel duplex storage device according to the present invention will be explained in more detail with reference to the drawings.

Set 1 Figure ti Parameter 1j Duplex storage device, storage control Kl cover forming part of the central processing unit, and O! It is a figure showing l continuation. @1 Figure (a) As shown in K, 5totL row duplication system all OFi@1 and Saba 10 memory scissors 1.2
, and a parallel control wheel [i, devices 3 and 4 are connected to the second storage control device 21, respectively, and
The third and fourth storage devices 3 and 4 connected to the storage control device 21 constitute a second parallel duplex storage device 11, which controls data. If we consider that the parallel control device 5 in Fig. 1(a) is included in the first storage control device 20, Fig. 1(a) F
It is also possible to consider it to be conceptually the same as FIG. 1(b). However, while the first storage control device 20Fi is connected to the first parallel duplex storage device 10 through one port (interface connection port), the second storage control device 21 is connected to the second parallel storage device 10 through two ports. It is connected to the parallel duplex storage device 11 of. Therefore, the number of boats for one storage control device 9 is smaller in FIG. 1 (1), which is advantageous in terms of configuration. On the other hand, in FIG. 1(a), since the parallel control device 5 is present between the first storage control device 20 and the first storage device 1 or the third storage device 2, the access time is not long. 1 (b).

The present invention is not limited to these configurations, and as mentioned above, it is possible to consider that FIGS. 1(a) and 1(b) are conceptually the same. The present invention will be explained below mainly by taking as an example a parallel dual storage device having the configuration shown in FIG. 1(1).

FIG. 2 is a block diagram showing the parallel control device 5 in more detail. In FIG. 2, the parallel side - device 5Fi 1st
1st to 4th parts 7a 31 to 34 for receiving signals from the storage control device 2, and fifth to sixth buffers ss for sending signals.

36, address counter @O, and a lot number control circuit 70
, an activation signal generation circuit sO, a first O0R gate 110 for transmitting the output of the first buffer 31 to the output REQ of the activation signal generation circuit IO, an instruction code generation circuit O, and an irises 1 to 1. 40th choice circuit 100. 120. 4
S, S%, the storage device instruction register 13, the S-th selection circuit 1sO controlled by the storage device instruction register 130, the data register 140 holding the output of the S-th selection circuit 150, and the first The seventh to ninth buffers 41 to 43 send signals to the 80th storage devices 1 and 2, the 11th to 13th buffers s1 to S3, and the first and second buffers send the read data. 2 storage device ll,
10th and 14th buffers 4 for receiving from 2
The lower bit CNT of the 0 interrupt control circuit 70d address counter @0, which is established from 4 and 54, is input, and the control signal I
NT, REF'.

The STA is activated by the activation signal generation circuit 9, the instruction code generation circuit Hatake O2, and the first to fourth selection circuits 100°120.4
5. Supply to 511 townships. To make the explanation easier to understand, the eighth storage device 2 has been disconnected from the system for some reason and only the first storage device 1 is operating normally, and in order to return to parallel duplex operation. Assume that it is necessary to transfer the contents of the first storage device 1 to the third storage device so that the stored contents of both devices match.

FIG. 3 is a diagram showing a one-time chart of some signals in the embodiment shown in FIG. Address counter 60 in FIG. 2 receives a clock signal from an external circuit 971 and is constantly counted up, and its output upper pit tom DDtlj is incremented by l every time T shown in FIG. In Figure 3, the time is shown as OT and the value of the 10 upper bits ADD [A]. On the other hand, the lower bit CNT#1 of the output of the address counter 60 is input to the interrupt control circuit 70. When the trigger signal TGO from the external control device is applied to the interrupt control circuit 1eK during the period between time OT and IT, the control signal 8TAC) state changes to 1 and 1) from the first storage device 1 after time IT. Second storage device! Heden's transfer begins. At the same time, the time interval between states ill of the control signal INT is expanded from time τ1 to time talc. As is clear from the control signal INTtj, this control signal IN is sent to the tenth storage control scissors 2JK via the sixth buffer 73.
10th memory control 1 until T returns to IK during IK summer running
The device ff 120 is controlled not to send any operation requests. The instruction code generation circuit 80 generates the first and third instruction codes CMI, CMI, and CMI by the control signals REF, ST, and the control signal MNO from the storage device instruction register 130.
CMj! generate.

The first instruction code CMIFi is used in the first storage device 1, and the second instruction code CM! It is used for the storage device 2 of. Storage device instruction register 130Fi is a 1-bit register that instructs from which storage device read data is to be sent to the storage control device 20 of M1. Since the first storage device is specified based on the above assumption, O is set by the external control device. First and second instruction code C
M.I.

The CM control signal may be set to any value while the control signal INT is O, and is indicated as %DON'T CARE# in FIG. The state of the control signal INT is 1 and the control signal is 8.
When Tm is O, a refresh command R@f is sent. On the other hand, when the state of the control signal 8TA is 1, depending on the state of the control signal MNO, a read command R@ad is sent to the front cow, a fresh command R@f is sent to the rear cow, or a refresh command is sent to the spindle and half. A write command 11@f is sent to the rear register. Now, if the state of the control signal MNO is O, as shown in FIG. 3, the instruction code CMI of @l is Read −+ R@f, and the first instruction code CM2 is R@f−+Write. It has become. However, when the control signal MNO is in the 1 state, the relationship between the first and second instruction codes CMI and CN3 is reversed. The start signal generation circuit sO receives a control signal INT.

It is. The starting signal generation circuit
Since it can be configured, the explanation is omitted in Details 1. 1st to 5th selection circuits 100, 120° 45.5 in the snow map! I
, 1B1) are all mushroom input type selection circuits, and when each control terminal 8 is in the state IK, a good signal is selected in addition to the lower input terminal in FIG. Therefore, when the control signal INTO state is 1, it is clear from FIG. selection circuit 46. and 5s are the first and second instruction codes CMI and CM from the instruction code generation circuit IO, respectively.
Select 2. Further, the second selection circuit 12 selects data set in the data register 141. Since it is assumed that the state of the control signal MNO is O, the S-th
The selection circuit 150 selects data from the first storage device via the first O buffer 44 .

As is clear from the above explanation, while the state of the control signal STm is O, the parallel control device 5 simultaneously refreshes both the first and second storage devices 1 and 2 with a period T.
A request is sent. When the control signal 5TAO state vagina is 1, the parallel control device 5 reads data from the first storage device 1 at a period T, sets it in the data register 140, and at the same time refreshes the first and second storage devices 2. That radio wave,
v7 data from the first storage device 1 and transfer it to the third storage device 2.
Write the data in the data register 14. That is, the first storage device IKs? The data at the designated address of the second storage device is transferred to the designated address of the second storage device, and the data at that address is matched between the first storage device 17 and the second storage device 2. When this operation is completed for all addresses JK, the interrupt control circuit 71 operates so that the state of the control signal 8T becomes - again, and from then on, parallel control is performed even if the state of the control signal INT becomes IK. Ren 15F'i 1st
And mackerel! 0 storage device 1. When the state of the control signal INT is O, no action is taken other than refreshing both the
Normal read requests and write requests are sent to Noto 11 from the first storage control Mffil'20. However, the control signal ST is controlled by the external IIO controller so that the state of the control signal ST can change from O to 1, and writing is always performed to both the first and second go memory devices. . When the control signal INTO state is 1, data is transferred regardless of the address of the write request in the first memory device 20, so data transfer from the first memory device 1 to the third memory device 1 is not possible. When writing from the storage control device 2 is performed to an address that has not been completed, the data at the 1,000 addresses match at that point.

Therefore, in principle, data transfer is not necessary after that. However, in the present invention, as is clear from the above description, when writing is performed from the first storage control device 20, the tenth storage device 1 and the second storage device 2 are transferred to each other at a certain address. Regardless of whether the contents match or not, the parallel controller S stabs all addresses and returns tII.
, l is configured to transfer data from the storage device 1 to the second storage device 2. However, it is possible to configure the parallel control device fIIs so that data transfer is omitted for addresses whose contents match. In this case, although the transfer time is reduced, the amount of hardware increases and control becomes complicated. Sometimes it can become much larger.

FIG. 4 shows a specific configuration example of the instruction code generation circuit 800 shown in FIG. 2. In FIG. @ In figure 4, ・Control signal 8
TA is a 4-person type sixth and seventh selection circuit 11m5,
The control signal REF and the control signal MNOII'i are input to the selection terminals SO and 51 of the sixth and seventh selection circuits 185 and 188, respectively. The 1st to 30th code generation circuits 1 to 1-s each have 7 Letssie codes, [output code, s? and write code, and
and 10th selection Omoji 115. l@IO input terminal AO-
AI, a certain i 11 first AND game) connect to 1117 and make a mistake. First selection time 12i111 (D output Fi#!2
OR game) 111, enter the first AND game) 11
Performs logical OR with rO output. As a result, the obtained circular OR is sent out as the first instruction code CMI. The output of the 10th selection path 186 is input to the OR gate 1 of Tuna 3,
A logical OR is performed with the output of the first AND gate 1-T.

As a result, the obtained logical sum is sent out as the second instruction code CM2. Next, the 6th and 70th selection-path 185
, 111@O The signal supplied to the selection terminal 80.81 is (
So, 81), the state of the signal appearing at the control terminal IK is 1, and (8@, 81) is (0, OL (o,
When 'L (1, '0), (11'')', the signals input to the input terminals Ae, AI, M!, and M3 are selected. Therefore, the state of the control I signal STA is 0.
When 0, the @th and TO selection circuits 1g5, 11I
The output state of 11Fi is always KO. On the other hand, the first AND
Gate IJIFi#! Since the input of the code generation circuit 181 of No. 1 is output as is, both the first and second instruction codes CMI and CMzt: are the refresh code and tk, and conversely, when the state of the No. 1 control signal 8 is 1, As is clear from the above description, the first and third instruction codes CMI and CMff are set to # according to the values of the control signals REF and MNO.
1! It is sent out as shown in figure m in Figure 6. It goes without saying that the instruction code generation circuit shown in detail in FIG. 4 can perform the operations described in FIG. 3.

FIG. 6 is a diagram illustrating in detail a specific example of the interrupt control circuit 10 shown in FIG. In FIG. 6, a decoder 71Vi inputs and decodes the lower bit (CNT) of the output of the address counter 60 in FIG. As a result of the decoding, the shape 1Ii1 is outputted sequentially from the output terminals co and at to tit at predetermined time intervals. Output terminals CD and CIFi of the decoder 11, as shown in FIG. 2nd~
The second and third AND gates 171, 17 are connected to the fourth AND gates 171, 172, 173 respectively, and the third flip-flop rough 40 output and the output of the counter 16 are connected to one input. These gates supply signals to the fourth flip clock 1TIO set terminal 8 and reset terminal R, respectively.

The output terminal Q of the 7 lip 70 knob 75 of the vehicle 4 is the long terminal Kli of the 4th and @6 gates 173.17g! It is also connected to the reset terminal R of the third standby flop 14. First, the output from the output terminal Q of the 7-lip block 1s @4 is sent to the outside as a control signal STA. -7 JO output terminal OFi is connected to the fifth and first gates 174.17@, and further connected to the clear terminal CL of the interrupt counter T1.

The count-up terminal CUK of the interrupt counter T is the fourth
1f) The count up signal from the AND gate 113 is added and the count number of the allocated lot number counter T@ reaches a predetermined value Kfi
Then, the state Ii1 is output from the output terminal CR. In the initial state, 11$11 and the fourth flop 7
4.75 are both KIJ-shaped mric, so the interrupt counter 1$ is also in the /Va state. On the other hand, the first and second 7-lip flops rz and rs are periodically set and reset, and are connected to the 417th) OR gate 1T via the sixth and seventh AND gates 178 and 176.
IKN and supply output. first flip-flop T
When the output of 2 is set, the pulse width of the control signal INT shown in FIG. 3 is i'i time twice. On the other hand, as is clear from FIG. 3, the output of the second flip-flop Ts is sent out as the control signal REF.

However, the OR of the control signal INTtfl14)17
It goes without saying that the output of 7 has the same waveform as the control signal REF in the initial state.

In the initial state, when the trigger signal TGO is input from the external control device, the nine logical product obtained by the fifth AND gate IT4 becomes 1, and thereby the third flip-flop T4
is set. Therefore, the output state S of the third flop 7w tube T4 becomes l. At this time, when the output terminal of the decoder 11 (jKl appears, the state of the output of the first-in-law AND gate 1T1 becomes 1), and the flip-flop 7% of the stripe 4 becomes (
will be cut. As a result, the states of the outputs of the outputs of the gate 5 and the sixth AND gate 174.1Tl become O), and the interrupt counter 1 is released from the tally state. Control signal STmuO
When the state becomes 1, the third flip-frog 74 is reset and the AND game 171 of mackerel 4 is opened. Therefore, the interrupt counter T@ is output from the output terminal C2 of the decoder T1.
Each time 1 appears in , it is counted up and the sixth AND game) 17B is opened. Therefore, the control signal I NT
i! It has the same waveform as the output of the first 7-lip 70-tube T1. When the interrupt counter T6 continues to count up and the count value reaches a predetermined value, that is, a value larger than the number of words of the Gai 1 and go storage devices in FIG. 2, Fil appears at the interrupt counter T@O output terminal CR. , No. 30A
ND gate 11 opens. As a result, decoder 7140
When 1 appears on the output terminal, the fourth flip-flop I
S is set, and the control f4I number BTAO state 11 becomes O and p1 interrupt control circuit Ti1t returns to the initial state IIK.

As is clear from the above explanation, it goes without saying that the circuit shown in FIG. 6 satisfactorily fulfills the intended purpose and the function explained in FIG. 3. Now, the present invention has been explained in detail above, but according to the present invention, the interrupt time is only slightly increased, the operation of the central processing unit is not affected at all, and the contents of the third storage device 2 are It is clear that we can match the storage IK of sugar l. In addition, the number of nodes increases compared to the case where the present invention is not adopted, but as is clear from the first intention, this is because the first to fourth selection circuits 100, 120.45
．． 5%, interrupt control circuit 7G, instruction code generation circuit 80
Since it is a small amount, it does not have a significant impact.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the configuration of a parallel duplex storage device according to the present invention, and FIG.
11(b) shows the 80th embodiment. The purpose of this drawing is a detailed plotter diagram of the embodiment shown in FIG. 1(1) according to the present invention, and in particular is a diagram showing a detailed block configuration of a parallel control device. The w4s diagram is a diagram illustrating a tie-setting diagram for the control signal shown in the first example. FIG. 4 is a plotter diagram showing details of one embodiment of the configuration of the instruction code generation circuit shown in FIG. 2 and used in the companion parallel control device. FIG. 5 is a diagram showing the relationship between the state of the control signal of the instruction code generation circuit shown in FIG. 4 and the instruction code. FIG. 6 is a boot diagram showing details of one embodiment of the configuration of one interrupt control circuit used in the parallel control device shown in FIG. 2. 1.2, 3, 4...Storage device 5, fist, parallel control device 10.11, e, parallel duplex storage device 20.21...Storage control device SO-@-address counter 10...Interrupt control Device 5O--Use instruction code generation circuit 130...-Storage device indicator register 90...Activation signal generation circuit 100.120. 43 55. 150. 185°1 $ art... selection circuit 141) φ.-data register 11-Ig, 41-44.51-54...1 buffer 11G, 118. 181. 177--...-O
R gate 187.171~1? @-...AND gate 184-
Flip-flop T6/exposure/interrupt counter of inverters 181-18S-... ;-code generation circuit 71...decoders 12-T5... Patent applicant Hisashi Inoro, Patent attorney, NEC Corporation Representative: Hisashi Inoro x□ 1 Figure (C1) Figure 4 Figure 5 Figure 26

Claims (1)

[Claims] I
Iffj - first and second for storing content information
a storage device, and a control device for controlling the loading or reading of information 1* with the same content to the pre-addresses of the first and second storage devices. In the parallel duplex storage device, the parallel storage device includes an address counter, an interrupt control circuit, and an instruction code generation circuit. The instruction code generation circuit comprises a storage device instruction register, a data register, a start signal generation circuit, a plurality of cylinder selection circuits, a plurality of cylinders of buffers, and one or more cylinders of OR gates; It is equipped with a code 4 power circuit for multiple tubes, a selection circuit for multiple tubes, an OR gate for I[teacher, an AND gate for tmt#'iI[teacher, and an inverter for 1lillfi or multiple tubes, and , the interrupt system m
The circuit is a decoder. An interrupt counter and a multi-tube 7 lip-flop. It is equipped with a plurality of AND gates and one or more OR gates, and the front interrupt control circuit sends out one number of control signals to define the first time width and the second time width. and the instruction code generating circuit inscribes the refresh command in the first and second storage devices corresponding to the first time width, and sends out a refresh command corresponding to half of the second time width. and sends a read command to the first storage device, and at the same time sends a 7 retrieval command to the second storage device, and in response to the manual operation of the second time width, a refresh command is sent to the [1 storage device]. A parallel duplex storage device, characterized in that it is configured to send a write command to the second storage device as well as to the second storage device.