GB2084768A - Circuit arrangement for rapidly exchanging data between the memory of an electronic processor and the interface units of its peripheral units - Google Patents

Abstract

A circuit arrangement for transferring data between a CPU and interface units comprises memory (CT) the cells of which are uniquely associated with interface units and in which the CPU writes the number of an assigned DMA channel. Four groups of registers addressed by the memory (CT), the (input or output, etc.) transfer characteristics, the address of the first cell, the magnitude of the central memory area employed for transfer purposes, and the number of transmitted words being written in one of the registers (that one connected to the channel). Control and operating circuits are provided. Two or more input interfaces can use the same channel and the address of each interface is automatically put ahead of their respective word. <IMAGE>

Description

SPECIFICATION Circuit arrangement for rapidly exchanging data between the memory of an electronic process and the interface units of its peripheral units The present intervention relates to a circuit arrangement which makes it possible to transfer data at high speed between peripheral interfaces and a memory in an electronic processor (DMA transfer). Each peripheral unit arranged to exchange information or dialogue with the processor is connected to a respective bidirectional interface unit or, preferably, to a pair of unidirectional (input and output) interfaces. A plurality of interfaces can be brought together in a circuit arrangement, termed a module, which may also comprise control circuits as well as circuits arranged to automatically operate or govern data transfer between one or more interfaces and the processor memory.

According to the present invention there is provided a circuit arrangement for rapidly transferring data between the memory of an electronic processor and the interface unit of peripheral units connected thereto (called "DMA") wherein channels are used for each transfer operation, the circuit comprising a memory each cell of which is uniquely related to an interface unit and initialled by a central unit (called "CPU"), by means of the number of the channel assigned to the DMA transfer, the said memory being addrssed by the interface units and addressing four groups of registers; a first group of registers each of which is initialled by the CPU by means of a control word indicating the characteristics of the DMA transfer performed on the channel to which the register belongs; a second group of registers each of which is initialled by the CPU by means of the address of the first cell of the memory area allocated to the channel to which the register belongs; a third group of registers each of which is initialled by the CPU by means of the number cells of the said memory area; a fourth group of registers each of which is initialled at "0" by the CPU and arranged to count the transfers effected on each channel; and operating and control means common to all channels designed to operate data transfer along each channel in accordance with the modalities written in a respective register of the first group by using the information stored in the respective registers of the second, third and fourth groups of registers.

A preferred circuit arrangement according to the invention has the following features:~ - two or more peripheral units can use the same channel to transfer their data to the same memory area; - each datum is automatically preceded by the address of the peripheral unit that has generated it; - transfer to the memory can be effected either by blocks (by sequentially occupying all the cells of the memory area allocated to that channel until it is completely filled) or cyclically, i.e.

by cyclically entertaining all the cells of the memory zone assigned to that channel; - for each input transfer (from a peripheral unit to the memory) it is possible to control in advance whether the memory cell is empty, should it be engaged, no transfer takes place; - both output and input channels can simultaneously exist; - allocation of each channel is performed by the CPU which also defines the characteristics of it (input or output, address of the first cell, dimensions of the memory area associated with it, etc.).

An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:~ Figure 1 is a block diagram of a circuit arrangement in accordance with the invention; Figure 2 is a diagram of an addressing circuit (IND) of the memory and the second, third and fourth group of registers; Figure 3 is a diagram of a cutting out circuit (SP) for the channel; Figure 4 is a block diagram of an operating or governing circuit (TD) of a double DMA transfer; and Figure 5 is a "truth table" of a possible control circuit for a control word.

With reference to Fig. 1, the procedure, termed DMA (direct memory access) below, of rapidly transferring data from memory to a peripheral unit is described.

In the present specification a "DMA channel" is defined as a group of registers and control circuits arranged to operate data transfer between one or more peripheral interfaces and a central memory buffer.

When an input or output peripheral unit asks to be connected to the central memory, the CPU assigns a free channel to it. To this end, the CPU writes the address of the peripheral unit in the register SCR and the channel number in the cell of the memory CT thus addressed. In the succeeding cycles the number of the channel addresses four registers CH, FLA, TRN and TRC (one for each of the four groups of registers indicated in the drawings by the same letters) in which the CPU writes: - the characteristics of the DMA in the register CH, as further described below; - the address of the central memory cell with which the memory zone assigned to the DMA begins, in the register FLA; - the length of such memory zone in the register TRN.

The register TRC stores the number of words transferred to each DMA channel and the CPU initials it to "O".

The data to be written in the memory CT and the registers CH, FLA and TRN are sent by the CPU by way of the output bus OB.

In a preferred embodiment, the groups of registers TRN and TRC comprise a random access memory (RAM) with 24-bit words, twelve bits being written in the registers TRN and the remaining in the registers TRC. Similarly, the groups of registers CH and FLA comprise a single random access memory (RAM) with 24-bit words, the first 18 bits (0 to 17) of each word, being written in the registers FLA and the remaining 6 bits (18 to 23) in the registers CH.

The latter bits have the following meaning: CH 23 = enabling of the channel to operate in DMA; CH 22 = output DMA (CH 22 = 1) or input DMA; CH 21 = single or double DMA (CH 21 = 1 )~each transfer occurs in two successive stages: in the first stage the address of the peripheral unit is stored, whereas in the second stage the datum is written; a double DMA is only possible as an input DMA and this occurs when the channel is used by a plurality of peripheral units; CH 20 = block or cyclic DMA (CH 20 = 1): during a cyclic DMA all the cells of the memory area can be cyclically used; CH 19 = enabling to ask for an interruption; should the memory area be empty during an output DMA, an enabled channel (CH 19 = 1) causes the interface to which the channel is assigned to generate an interruption request for the CPU; CH 18 = DMA controlling the availability of a free memory cell; this is of particular importance in the case of cyclic DMA and will be discussed later on.

Carrying out of an input or output DMA cycle with or without control.

When a interface asks the CPU to transfer a word by DMA, its address I written by the CPU in the register PRR causes the memory CT to make the number of the channel, assigned to the interface, available on its output. Such a number addresses the four registers connected to the channel. In a first stage, the adding circuit S adds the contents of the registers FLA and TRC to obtain the address of the memory location concerned with the transfer operation and to send it to the CPU by way of input bus IB. At the same time, the content of the register TRC is written in the counter C which is stepped forward by one and its content is compared with the content of the register TRN by the comparator COMP.Should the memory area assigned to channel be full (TRN = TRC), the comparator generates a signal EOB which, among other things, disables the gate P, thereby setting the content of the register TRC to 0. This allows correct addressing in the case of circular DMA. If input DMA is taking place with control (CH 18 = 1), the CPU checks whether the memory location is free and, should the memory be engaged, the CPU: - prevents the addressing circuit IND, illustrated in Fig. 2, from generating a writing signal WTC which transfers the content of the counter C to the register TRC; the interface will consider the DMA cycle as not performed and the content of the register TRC is not increased; - disables the channel DMA by acting on the cutting out circuit SP illustrated in Fig. 3; - inhibits the second cycle of a double DMA by acting on its respective operating circuit TD illustrated in Fig. 4.

If an output DMA is being performed with control and the memory area is empty, the CPU: - prevents the content of the transfer counting register TRC from increasing as was the case with the input DMA; - if the channel is enabled to signal an interruption (CH 19 = 1) the CPU prevents the calling registers for the interface from being set to zero (and thus the interface keeps its request); - if the channel is not enabled to signal an interruption (CH 19 = 0) the CPU disables the interface to forward further calls.

The interface circuits IP concerned are not described as they are well known to a person skilled in the art and in any case they do not form a part of the present invention.

Carrying out of a double DMA A double DMA in which the address of an interface and a word coming from the interface are stored in two successive cycles, is normally used when a plurality of interfacesa operate on the same channel by loading their data on a single memory area. This is typically an input DMA with control.

In the first cycle, the operating circuit TD (Fig. 4) generates a signal DCY which causes the interface address written in the register PRR to be trnsferred to the memory. The same signal stored in the circuit TD, enables the second cycle to be carried out in accordance with the same modalities previously described with reference to the input DMA with control. More particularly, the register TRC is stepped forward, which makes the channel available for another DMA cycle.

The drawings diagrammatically illustrates the following operating and control circuits: - a circuit IND designed to receive timing signals and addresses (generally indicated by WI) from the CPU and to generate writing signals for a memory (WCT) and the groups of registers (WCH, WFLA, WTC, WTN); - a circuit SP arranged to receive timing and enabling signals (generally indicated by WA) from the CPU, some bits (generally indicated by CH) from the register CH, and a signal EOB (complete memory) from a comparator COMP and to generate the CH 23 bit value (channel on or off) at each DMA cycle; - a circuit TD designed to receive instructions and information (generally indicated by WR) from the CPU and a CH 21 bit (single and double DMA) from the register CH, and to generate a signal DCY which controls the carrying out of the second cycle of a double DMA.

It should be noted that the data (and the address of the peripheral units during the first cycle of a double DMA) transferred from the CPU to the interfaces IP are transmitted along buses IB or OB depending upon whether one is dealing with input or output DMA. The CPU also initials the memory CT and the registers CH, FLA, TRN, TRC by way of the bus OB.

Fig. 2 shows an embodiment of an addressing circuit IND.

The memory CT and the registers FLA and TRN are exclusively written during the channel initialization stage. Respective writing signals WCT, WFLA and WTN are generated by the gates 2, 3 and 4 enabled by the output timing signals of the gate 1 which receives a strobe signal SPB and its clock signal PBCK on its inputs in response to addressing control signals ICHAT, IFLA, ITRN. The Register CH is initialled together with the register FLA in the case in which, as it happens in a preferred embodiment of the invention, they are allocated to a single RAM in which the CPU can write the initial content of the two registers as a single word. The register CH, however, is enabled at each DMA cycle to allow the cutting out circuit SP (Fig. 3) to cut off the channel by having CH 23 = O.Thus, the writing signal WCH is generated by a first adding circuit 11 which receives a writing signal WFLA and a signal WDMA (writing order during a DMA cycle) on its inputs.

The register TRC can be initialled to "0" simultaneously with the register TRN and must also be enabled at each DMA cycle to receive the content of the counter CONT by stepping forward by 1, unless a signal MO is present which indicates that the CPU has found that the memory cell, in which the peripheral unit is going to write, is engaged. The writing signal WTC generated by the gate 5 and the second adder 12 satisfies the above mentioned conditions.

All the input signals (SPB, PBCK, CHAT, IFLA, ITRN, MO. WDMA) for the addressing circuit IND are generated by the CPU. Fig. 3 shows an embodiment of the cutting out circuit SP for the DMA channel.

It is necessary to cut off the channel (CH 23 = 0), when in a block DMA (CH 20 = 0) the memory capacity (EOB = 1) is exhausted, or when in an input DMA (CH 22 = 0) the CPU detects the fact that the memory is engaged (MO = 1). The circuit comprising the gates 6 and 7 and the adder 13 satisfies the above conditions. One should note that, in the case of an input cyclic DMA, should the writing speed be higher than the reading speed, the CPU detects the fact that the memory is saturated (MO = 1) and cuts off the channel. The cutting out circuit SP also comprises a bistable 31 timed by a clock TRCK which receives, on its data input, the CH 23 bit generated by the register CH.The inverting output of the bistable 31 is connected to an input of a multiplexer MTX whose further inputs are respectively connected to the output bus OB and a fixed polarity, whereas its output is connected to the register CH. The signal available at the output of the multiplexer is written in the cell CH 23 in response to the writing signal WCH.

The multiplexer MTX is controlled by the output signal of the adder 13 and a second DMA signal indicating that a DMA cycle is being performed. Upon initialization, no DMA occurs and the multiplexer connects the input of register CH to the bus OB without taking into account the signal available at the output of the adder 31.

During a DMA cycle, should it be necessary to cut off the channel, the output of the gate 13 switches to "1" and writes a positive polarity in the cell CH 23.

Should the register CH comprise an RAM, the latter acts as an inverter. In this case the bit CH 23 generated by the register CH is "0" which conventionally means that the channel is cut off.

Normally, CH 23 = 1 available at the output of the RAM is transferred at each stroke of the clock TRCK as an "0" to the input of the multiplexer which loads it in the RAM CH which still generates "1" on its output.

Without departing from the scope of the present invention, it is possible to modify in a way clearly apparent to a person skilled in the art the cutting out circuit described above even by changing the number and/or the kind of events which cause the cutting off of the channel (CH 23 = 0).

Fig. 4 illustrates an embodiment of the circuit TD which operates the double DMA in accordance with the previously described procedure.

In a preferred embodiment thereof, the CPU answers to any request from the interface by generating a signal ASW which enables to carry out all the request. In particular, the CPU controls, by means of the signal ASW, the interface to have access to the memory, in the case of DMA.

Should a double (CH 21 = 1) DMA (DMA= 1) being performed and the peripheral unit be single or enjoy priority (PR = 1) among those requesting access to the DMA channel, the gate 8 enables the signal ASW to be forwarded, similarly to the signal DCY, to the CPU to control availability of the memory cell addressed by the adder S (Fig. 1) before transferring to it the address of the peripheral unit from the register PRR. The signal DCY is stored by the clock lOCK in the bistable 32 whose output DCYFF replaces the signal ASW in the second DMA cycle which is a standard input DMA with control.

Non-availability of free memory areas (MO = 1) in the first cycle causes resetting of the bistable 31, whereas in the second cycle it prevents the register TRC from increasing, as specified with reference to Fig. 2.

In the embodiment shown in the drawings, the signals ASW or DCYFF are stored in the bistable 33. Should the memory be full (MO = 1), the signal DCYFF disappears and also disappears the signal ASWFF at the successive stroke of the clock IOCK.

Fig. 4 illustrates the case in which the signal ASW is provided. Should such a signal be eliminated, the adder 14 and the bistable 33 can be omitted.

A circuit arrangement in accordance with the present invention can also comprise means for controlling whether the controls (CH 18 to CH 22) written in the register CH by the CPU are compatible. The stucture of such controlling means is closely related to the types of procedure forseen for the DMA. The table in Fig. 5 applies in the case in which the following procedure are not allowed: Double output DMA E = CH 21. CH 22 Double input DMA without control ~~~~~~~~~~~~~~ E=CH 18.CH 21.CH 22=CH 21 CH 18+CH 22 Input DMA not enabled to ask for an interruption E=CH 19.CH 22=CH 19+CH 22 An abnormal state (E = 1) is signalled to the CPU.

The control means may comprise AND and OR logic circuits, or according to a preferred embodiment of the invention an ROM (read-only memory) addressed by the CH 18 to CH 22 bits and enabled by the CH 23 bit (no control is required when the channel is cut off). The logic values of E are written in the cells of the ROM according to the table in Fig. 5 or tables similar to it if the non-allowed combinations differ from those indicated above.

An interesting variation is that of causing the control means to generate a control signal, unless the channel is cut off (CH 23 = 0). In this case the truth table can be obtained from that of Fig. 5 by replacing the logic values in column E with complementary values.

Claims (12)

1. A circuit arrangement for rapidly transferring data between the memory of an electronic processor and the interface unit of peripheral units connected thereto (called "DMA") wherein channels are used for each transfer operation, the circuit comprising a memory each cell of which is uniquely related to an interface unit and initialled by a central unit (called "CPU"), by means of the number of the channel assigned to the DMA transfer, the said memory being addressed by the interface units and addressing four groups of registers; a first group of registers each of which is initialled by the CPU by means of a control word indicating the characteristics of the DMA transfer performed on the channel to which the register belongs; a second group of registers each of which is initialled by the CPU by means of the address of the first cell of the memory area allocated to the channel to which the register belongs; a third group of registers each of which is initialled by the CPU by means of the number of cells of the said memory area; a fourth group of registers each of which is initialled at "0" by the CPU and arranged to count the transfers effected on each channel; and operating and control means common to all channels designed to operate data transfer along each channel in accordance with the modalities written in a respective register of the first group by using the information stored in the respective registers of the second, third and fourth groups of registers.

2. A circuit arrangement as claimed in claim 1, wherein the said operating and control means comprise first means arranged to generate, for each channel, the address of the memory cell concerned with the DMA transfer; second means designed to increase by one, channel by channel, the respective register of the fourth group as well as to detect when the memory area associated with each channel is filled by setting to O a respective register of the fourth group; third means arranged to enable writing in the memory and the fourth groups of registers; fourth means arranged to inhibit a channel in the absence of cells available in the memory area associated with the channel; and fifth means arranged to operate a double DMA transfer in which each word written in the memory by a peripheral unit is preceded by the address of peripheral units itself.

3. A circuit arrangement as claimed in claim 2, wherein the first means compise a circuit arranged to add the content of a respective register of the fourth group to the content of the register of the second group and to transmit the address thus obtained to the CPU by way of the input data bus.

4. A circuit arrangement as claimed in claim 2, wherein the said second means comprise a counter arranged to receive the content of a respective register of the fourth group and to cause it to step forward by one; a comparator arranged to compare the output of the counter with the content of the respective register of the third group, thereby generating a first signal in case of identity; and a gate disabled by the first signal and having its input connected to the output of the counter and its output connected to the fourth register.

5. A circuit arrangement as claimed in claim 2, wherein the third means comprise a first gate whose input receives a strobe signal and a respective clock in the initialization step of the registers; second, third and fourth gates enabled by the output of the first gate and arranged to generate respective writing signals for the memory and the second and the third group of registers in response to address controls generated by the CPU; a fifth gate disabled by a second signal available if the memory cell addressed by the second means is engaged, the input of the fifth gate receiving a writing control signal during a DMA cycle; a first adder connected to the output of the third gate and to the input of the fifth gate for generating the writing signal of the first group of registers; and a second adder connected to the output of the fourth and fifth gates for generating the writing signal of the fourth group of registers.

6. A circuit arrangement as claimed in claim 2, wherein the fourth means comprise a first bistable arranged to receive on its data input the bit of the control word indicating enabling of the DMA: a multiplexer having a first input connected to the output of the first bistable, and a second input connected to a fixed polarity and its output connected to the input of the first register; and a third adder having its inputs connecting to the outputs of sixth and seventh gates whose inputs receive the first signal and the bit of the control word indicating that a block DMA is being carried out, a respective second signal and the bit of the second control word indicating that the input DMA is being carried out, the output of the third adder controlling the multiplexer.

7. A ciruit arrangement as claimed in claim 6, wherein the multiplexer connects its output to a third input connected to the output bus in response to the absence of a third signal available if a DMA transfer is being performed.

8. A circuit arrangement as claimed in claim 2, wherein the fifth means comprise an eighth gate arranged to receive at its inputs the third signal, the bit of the control word indicating that a double DMA is being carried out, and a fourth signal available if no peripheral unit having a higher priority asks for engaging the DMA channel, the output of the eighth gate controlling the CPU to check whether a memory cell is free before writing in it the address of the peripheral unit stored in the fifth register, such an address being also applied to the input of a second bistable reset by the second signal whose output enables the second cycle of the double DMA.

9. A circuit arrangement as claimed in claim 8, wherein the eighth gate is enabled by a fifth signal generated by the CPU in response to a DMA request, and the fifth signal is added to the output of the second bistable before being applied to the input of a third bistable.

10. A circuit arrangement as claimed in claim 1, which comprises sixth means designed to check the mutual capabiity of the conrol word bits by generating an alarm signal.

11. A circuit arrangement as claimed in claim 10, wherein the sixth means comprise a readonly memory enabled by the bit indicating enabling of the DMA channel and addressed by the other control word bits, the cells of the memory storing the logic values of the alarm signal in accordance with a predetermined "truth table".

12. A circuit arrangement substantially as hereinbefore described with reference to the accompanying drawings.