JPS58157135A - パタ−ン形成方法 - Google Patents

パタ−ン形成方法

Info

Publication number
JPS58157135A
JPS58157135A JP57041273A JP4127382A JPS58157135A JP S58157135 A JPS58157135 A JP S58157135A JP 57041273 A JP57041273 A JP 57041273A JP 4127382 A JP4127382 A JP 4127382A JP S58157135 A JPS58157135 A JP S58157135A
Authority
JP
Japan
Prior art keywords
radiation
sensitive resin
forming method
pattern forming
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57041273A
Other languages
English (en)
Japanese (ja)
Other versions
JPH035653B2 (enrdf_load_html_response
Inventor
Masaru Sasako
勝 笹子
Kazuhiko Tsuji
和彦 辻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57041273A priority Critical patent/JPS58157135A/ja
Publication of JPS58157135A publication Critical patent/JPS58157135A/ja
Publication of JPH035653B2 publication Critical patent/JPH035653B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP57041273A 1982-03-15 1982-03-15 パタ−ン形成方法 Granted JPS58157135A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57041273A JPS58157135A (ja) 1982-03-15 1982-03-15 パタ−ン形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57041273A JPS58157135A (ja) 1982-03-15 1982-03-15 パタ−ン形成方法

Publications (2)

Publication Number Publication Date
JPS58157135A true JPS58157135A (ja) 1983-09-19
JPH035653B2 JPH035653B2 (enrdf_load_html_response) 1991-01-28

Family

ID=12603828

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57041273A Granted JPS58157135A (ja) 1982-03-15 1982-03-15 パタ−ン形成方法

Country Status (1)

Country Link
JP (1) JPS58157135A (enrdf_load_html_response)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100563242B1 (ko) * 1999-12-02 2006-03-27 액셀리스 테크놀로지스, 인크. 자외선(ｕｖ)에 의한 포토레지스트의 화학 개질법
US8039399B2 (en) 2008-10-09 2011-10-18 Micron Technology, Inc. Methods of forming patterns utilizing lithography and spacers
US8409457B2 (en) 2008-08-29 2013-04-02 Micron Technology, Inc. Methods of forming a photoresist-comprising pattern on a substrate
US9076680B2 (en) 2011-10-18 2015-07-07 Micron Technology, Inc. Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array
US9653315B2 (en) 2008-12-04 2017-05-16 Micron Technology, Inc. Methods of fabricating substrates
US9761457B2 (en) 2006-07-10 2017-09-12 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US10151981B2 (en) 2008-05-22 2018-12-11 Micron Technology, Inc. Methods of forming structures supported by semiconductor substrates

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100563242B1 (ko) * 1999-12-02 2006-03-27 액셀리스 테크놀로지스, 인크. 자외선(ｕｖ)에 의한 포토레지스트의 화학 개질법
US9761457B2 (en) 2006-07-10 2017-09-12 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US10096483B2 (en) 2006-07-10 2018-10-09 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US10607844B2 (en) 2006-07-10 2020-03-31 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US11335563B2 (en) 2006-07-10 2022-05-17 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US11935756B2 (en) 2006-07-10 2024-03-19 Lodestar Licensing Group Llc Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US10151981B2 (en) 2008-05-22 2018-12-11 Micron Technology, Inc. Methods of forming structures supported by semiconductor substrates
US8409457B2 (en) 2008-08-29 2013-04-02 Micron Technology, Inc. Methods of forming a photoresist-comprising pattern on a substrate
US8039399B2 (en) 2008-10-09 2011-10-18 Micron Technology, Inc. Methods of forming patterns utilizing lithography and spacers
US9653315B2 (en) 2008-12-04 2017-05-16 Micron Technology, Inc. Methods of fabricating substrates
US9076680B2 (en) 2011-10-18 2015-07-07 Micron Technology, Inc. Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array

Also Published As

Publication number Publication date
JPH035653B2 (enrdf_load_html_response) 1991-01-28

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