JPS58147052A - Multi-structural hybrid integrated circuit - Google Patents

Multi-structural hybrid integrated circuit

Info

Publication number
JPS58147052A
JPS58147052A JP57028480A JP2848082A JPS58147052A JP S58147052 A JPS58147052 A JP S58147052A JP 57028480 A JP57028480 A JP 57028480A JP 2848082 A JP2848082 A JP 2848082A JP S58147052 A JPS58147052 A JP S58147052A
Authority
JP
Japan
Prior art keywords
hybrid
leads
lead
child
thick film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57028480A
Other languages
Japanese (ja)
Inventor
Seiji Takeuchi
武内　省二
Masatoshi Tanaka
正敏 田仲
Minoru Ueda
穣 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP57028480A priority Critical patent/JPS58147052A/en
Publication of JPS58147052A publication Critical patent/JPS58147052A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3447—Lead-in-hole components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/368—Assembling printed circuits with other printed circuits parallel to each other

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

PURPOSE:To increase the IC mount density as a multi-structure by a method wherein some of the leads of a slave hybrid IC are fixed on the substrate of a master hybrid IC, after lead through-holes are opened on the master hybrid IC and the leads of the slave hybrid IC are inserted into these through-holes. CONSTITUTION:A conductor pattern, a resistance pattern, a glass pattern, etc. are repeatedly printed in thick film on a ceramic thick film substrate into a master hybrid IC element 1. For a slave hybrid IC element 2, a conductor, a resistor, a glass pattern, etc. are repeatedly printed in thick film on a ceramic thick film printed substrate, and it is placed on the element 1. Thereat, a plurality of leads 3 and 4 which project downward at equal intervals are planted on the both sides right and left of the elements 1 and 2, and the through-holes 7 to insert the leads 4 of the element 2 are provided on the element 1. Thus, the leads 4 which are required are pushed into the holes 7 and fixed by solder 9, and accordingly the projected leads 4 are connected to the leads 3.

Description

【発明の詳細な説明】 この発明は、複数個のハイブリッドＩＣを１個のハイブ
リッドＩＣとした多重構造ハイブリッドｔＣに係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-structure hybrid TC in which a plurality of hybrid ICs are combined into one hybrid IC.

ハイブリッドＩＣは、セラミック厚膜印刷基板の上へ、
抵抗、導体、ガラスなどのペーストを何層にも繰返し厚
膜印刷して回路を構成し、さらにコンデンサチップ、半
導体ＩＣチップ、必要なら抵抗チップなどを適当な導体
パターンの間にハンダ接合したものである。Hybrid IC is placed on ceramic thick film printed substrate,
A circuit is constructed by repeatedly printing thick layers of paste such as resistors, conductors, and glass, and then soldering capacitor chips, semiconductor IC chips, and if necessary resistor chips between appropriate conductor patterns. be.

ハイブリッドＩＣにおいて、回路の密度を上げるために
、ガラス層を介して、何回も導体パターンを多層に印刷
し、多層配線方式をとっている。In order to increase circuit density in hybrid ICs, conductive patterns are printed in multiple layers through glass layers to create a multilayer wiring system.

回路の密度を高めるには、かさ高いチップ部品を少くし
、配線幅を狭くし、抵抗の面積を減すことなどが考えら
れる。Possible ways to increase circuit density include reducing the number of bulky chip components, narrowing the wiring width, and reducing the area of resistors.

これらの事は、すでに広く実行されているが、コンデン
サ、半導体チップ等は回路の目的により、成る程度必要
であるし、全くなくす、というわけにはゆかない。These things are already widely practiced, but capacitors, semiconductor chips, etc. are necessary to some degree depending on the purpose of the circuit, and cannot be completely eliminated.

配線のｉは、厚膜印刷の精度を高めることにより、より
細くすることができる。しかし、配線（導体パターン）
の占める面積は、・実際のハイブリッドＩＣに於て、そ
れほど大きいという°ものではない。線幅を細くする事
によって、余分な面積が生ずる、という事は少ない。む
しろ、抵抗パターンの占める面積の方が問題である。　
　　　　　゛抵抗パターンは、抵抗用のペーストを厚膜
印刷して厚膜印刷基板主に作られる。抵抗値は、非常に
広い範囲の値のものをカバーしなければならないから、
比抵抗の異なる数種類の抵抗ペーストを用いる。つまり
、抵抗の印刷は、その抵抗ペーストの種類の数だけ繰返
し行われる。また、抵抗パターンは、印刷しただけでは
所望の値を実現することが難しい。抵抗を印刷した後、
サンドブラスト、レーザー光などで抵抗をトリミングし
なければならない。The i of the wiring can be made thinner by increasing the precision of thick film printing. However, wiring (conductor pattern)
The area occupied by the hybrid IC is not that large in an actual hybrid IC. Reducing the line width rarely creates extra area. Rather, the area occupied by the resistor pattern is more of a problem.
゛Resistance patterns are mainly made on thick film printed circuit boards by thick film printing of resistor paste. Since resistance values must cover a very wide range of values,
Several types of resistance pastes with different specific resistances are used. In other words, printing of the resistor is repeated as many times as there are types of resistor paste. Furthermore, it is difficult to achieve a desired value by simply printing a resistance pattern. After printing the resistor,
Resistors must be trimmed by sandblasting, laser light, etc.

このような訳で、抵抗は、多層印刷して重ねる事ができ
ない。必ず一層になる。しかも、一般に抵抗パターンは
ひとつひとつが広い。For this reason, resistors cannot be printed and stacked in multiple layers. It will definitely become more. Moreover, each resistance pattern generally has a wide range.

ガラスペーストを印刷して、多層化できるのは。Can you print glass paste and create multiple layers?

結局導体パターン（配線）だけである。In the end, it is just a conductor pattern (wiring).

配線だけ多層化したところで、チップ部品、抵抗の多層
化ができないかぎり、ハイブリッドＩＣの高密度化には
自づから限°界がある。Even if only the wiring is multilayered, unless chip components and resistors can be multilayered, there is a limit to how high the density of hybrid ICs can be increased.

また、このように、印刷回数を増やす高密度化への試み
は、印刷工程が増え、誤差が増えて、結局、製品になる
歩留りが悪化する、という難点を克服することができな
い。In addition, attempts to increase the density by increasing the number of times of printing cannot overcome the drawback that the number of printing steps increases, errors increase, and the yield of products deteriorates.

回路構成を高密度化すると、一般にリードの数も増加す
る場合が多い。しかし、リードの間隔はあまり狭（する
事ができない。多くの場合、リードの隣接間隔は２．５
ｍ程度である。リードを増すには、厚膜印刷基板の長さ
を増さざるをえなくなる。これは、必ずしも望ましいこ
とではない。Increasing the density of a circuit configuration generally often results in an increase in the number of leads. However, the spacing between the leads cannot be very narrow. In many cases, the spacing between adjacent leads is 2.5
It is about m. Increasing the lead necessitates increasing the length of the thick film printed circuit board. This is not necessarily desirable.

本発明はこのような難点を解決することを目的とする。The present invention aims to solve these difficulties.

結局、ひとつの厚膜印刷基板で高密度化することはこれ
以上難しい。。しかし、ＩＣとし１うのは、多くの場合
平板状であり、リードをプリント基板などにハンダづけ
して、回路の中へ組入れられる。よく考えてみれば、Ｉ
Ｃの上方は空Ｌ１ている場合が多い。ＩＣの面積に比し
て、能動素子、又は単位回路の数が、どれほどであるか
？　とＧ１う事で、ＩＣの実装密度を評価するが、これ
は、ＩＣが、プリント基板上へ平面的、つまり二次元的
に取付けられる事に対応している。In the end, it is difficult to increase the density using a single thick film printed circuit board. . However, in most cases, an IC is in the form of a flat plate, and its leads are soldered to a printed circuit board or the like and incorporated into a circuit. If you think about it, I
There is often an empty space L1 above C. How many active elements or unit circuits are there compared to the area of the IC? The mounting density of the IC is evaluated by G1, which corresponds to the fact that the IC is mounted flatly, that is, two-dimensionally, on the printed circuit board.

本発明者は、この点に着目し、ハイブリッドＩＣを多重
構造にすることにより無理なく実装密度を上げることが
できる、という着耀を得た。The present inventor has focused on this point and has found that it is possible to increase the packaging density without difficulty by forming the hybrid IC into a multiplexed structure.

本発明のハイブリッドＩＣは、親ハイブリッドＩＣにリ
ード通し穴を穿ち、子ハイブリッドＩＣのリードを、親
ハイブリッドＩＣのリード通し穴へ挿通し、親子ハイブ
リッドＩＣを一体化したものである。The hybrid IC of the present invention is one in which a parent hybrid IC is made with a lead through hole, and a lead of a child hybrid IC is inserted into the lead through hole of the parent hybrid IC, thereby integrating the parent and child hybrid IC.

以下、図面によって、本発明の構成、作用及び効果を説
明する。Hereinafter, the configuration, operation, and effects of the present invention will be explained with reference to the drawings.

第１図は本発明の実施例にかかる多重構造）１イブリツ
ドＩＣの斜視図である。第２図は第１図中の１−１断面
図を示す。FIG. 1 is a perspective view of a multiple hybrid IC according to an embodiment of the present invention. FIG. 2 shows a 1-1 sectional view in FIG. 1.

親ハイブリッドＩＣＩは、セラミック厚膜基板上に、導
体パターン、抵抗パターン、ガラスノずターンなどを繰
返し厚膜印刷したものである。コンデンサチップ、半導
体ＩＣチップなども、ノ＼ンダ付けされている場合もあ
る。厚膜印刷回路の構成は任意である。印刷回路は、第
１図に於て、基板の裏面に、或は表面に構成されている
が、ここでは図示しない。The parent hybrid ICI is a product in which a conductor pattern, a resistor pattern, a glass nozzle pattern, etc. are repeatedly thick-film printed on a ceramic thick-film substrate. Capacitor chips, semiconductor IC chips, etc. may also be soldered. The configuration of the thick film printed circuit is arbitrary. Although the printed circuit is constructed on the back side or the front side of the substrate in FIG. 1, it is not shown here.

子ハイブリッドＩＣ２は、親ハイブリッドＩＣ１の上方
に設けられる。同様に、子ハイブリッドｘｃ２は、セラ
ミック厚膜印刷基板の上に、導体、抵抗、ガラスのパタ
ーンを繰返し、厚膜印刷したものである。必要があれば
、チップ部品が、配線上にハンダ付けされている。Child hybrid IC2 is provided above parent hybrid IC1. Similarly, the child hybrid xc2 is a ceramic thick film printed substrate with repeated patterns of conductors, resistors, and glass printed in a thick film. If necessary, chip components are soldered onto the wiring.

親ハイブリッドＩＣ１の、左右両側には、複数本のリー
ド３が平行に設けられる。この例では、ＤＩＰ型（Ｄｕ
ａｌ　Ｉｎ　Ｌｉｎｅ　Ｐａｃｋａｇｅ　：　　デュア
ルインラインパッケージ）のリード形式となっている。A plurality of leads 3 are provided in parallel on both left and right sides of the parent hybrid IC 1. In this example, DIP type (Du
The lead format is dual in line package (al in line package).

すなわち、親ハイブリッドＩＣリード３は、左右平行二
列に等間隔に、基板と垂直になるよう設けられている。That is, the parent hybrid IC leads 3 are provided in two parallel rows on the left and right at equal intervals and perpendicular to the substrate.

親ハイブリッドＩＣＵ−ド３は、基板上の回路の配線へ
接続される電極（う、ンド：図示せず）に裏面でハンダ
付け５されている。The parent hybrid ICU card 3 is soldered 5 on the back side to an electrode (not shown) that is connected to the circuit wiring on the board.

子ハイブリッドＩＣ２の、左右両側にも、複数のリード
４が平行に設けられ、ハンダ付け６されている。A plurality of leads 4 are provided in parallel on both left and right sides of the child hybrid IC 2 and are soldered 6.

親″イブリッドＩＣリード３、子ハイブリッドＩ　ＣＩ
Ｊ−ド４の隣接リード間距離は一定で、例えば２．５５
５ｇ程度である。Parent “hybrid IC lead 3, child hybrid I CI
The distance between adjacent leads of J-Do 4 is constant, for example 2.55
It is about 5g.

しかし、平行なリード列の間隔は、親ハイブリッドＩＣ
リード３は広く、子ハイブリッドＩ　ＣＩＪ−ド４は狭
くなっている。However, the parallel lead row spacing is
Lead 3 is wide and child hybrid ICIJ-de 4 is narrow.

以上の構成は、ハイブリッドＩＣの周知の構成にすぎな
い。The above configuration is just a well-known configuration of a hybrid IC.

本発明に於て、新ハイブリッドＩＣ１に、子ハイブリッ
ドＩＣリード４に対応する位置へ、リード通し穴７が穿
たれている。リード通し穴７は、予め、セラミック白基
板の段階で穿っておくとよい。In the present invention, a lead through hole 7 is bored in the new hybrid IC 1 at a position corresponding to the child hybrid IC lead 4. It is advisable to drill the lead through holes 7 in advance in the ceramic white substrate stage.

子ハイブリッドＩＣ２のり−ド４は、親ハイブリッドＩ
Ｃ１の上方から、４リ一ド通μ穴７へ挿通し、親、子ハ
イブリッドＩＣＩ、２を一体化する。Child hybrid IC2 board 4 is parent hybrid I
Insert the four leads into the μ-hole 7 from above C1, and integrate the parent and child hybrid ICIs 2.

このため、子ハイブリッドＩＣリード４を、リード通し
穴７の近傍へ印刷した電極パターン８へ結合ハンダ９に
よりハンダ接合する。実際には、ハンダペーストを印刷
しておき、ここへ子ハイブリッドＩＣリード４を挿通し
、リフロー炉へ入れて加熱固化して、ハンダ接合する。For this purpose, the child hybrid IC lead 4 is soldered to the electrode pattern 8 printed near the lead through hole 7 using a bonding solder 9. Actually, a solder paste is printed, the secondary hybrid IC lead 4 is inserted therein, the paste is placed in a reflow oven, and the paste is heated and solidified to perform soldering.

子ハイブリッドＩＣリード４は、多数あるので、全てを
、親ハイブリッドＩＣＩへ固定する必要は′ない。子ハ
イブリッドＩＣリード４の内、非結合リード４ａは、単
にリード通し穴７へ挿入しであるだけである。Since there are a large number of child hybrid IC leads 4, it is not necessary to fix all of them to the parent hybrid ICI. Among the child hybrid IC leads 4, the uncoupled leads 4a are simply inserted into the lead through holes 7.

結合リード４ｂは、電極パターン８へ結合ハンダ９で固
着することができるが、この場合、もしも、結合リード
４ｂ　と、親ハイブリッドＩＣリード３のいずれかひと
つが共通リードであれば、つまり、導体配線でつながっ
ているリードであれば、いずれか一方を切りとって、取
り除いても良い。The bonding lead 4b can be fixed to the electrode pattern 8 with bonding solder 9, but in this case, if either the bonding lead 4b and the parent hybrid IC lead 3 are a common lead, that is, the conductor wiring If the reeds are connected, you can cut one of them and remove it.

さらに、結合リード４ｂは、必ずしもハンダ接合して、
親ハイブリッドＩＣｉに固着しなくてもさしつかえない
。かわりに、適当な接着剤を使って、結合リード４ｂと
、親ハイブリッドＩＣＩとを接着してもよい。この−場
合、リード通し穴フの周囲に電極パターンを、予め、印
刷しておく必要かない。Furthermore, the coupling lead 4b is not necessarily soldered.
There is no problem even if it does not adhere to the parent hybrid ICi. Alternatively, a suitable adhesive may be used to adhere bonding lead 4b and parent hybrid ICI. In this case, there is no need to print an electrode pattern around the lead hole in advance.

本発明に於て、親ハイブリッドＩＣＩと、子ハイブリッ
ドＩＣ２とは、子ハイブリッドＩＣリード４によって、
電気的に接続することができるが、電気的に共通なリー
ドは、本発明の要件ではない。In the present invention, the parent hybrid ICI and the child hybrid IC 2 are connected to each other by the child hybrid IC lead 4.
Although electrically connected, electrically common leads are not a requirement of the present invention.

全ての子ハイブリッドＩＣリード４が、完全に親ハイブ
リッドＩ　、Ｃの回路から独立していても差支えない。All the child hybrid IC leads 4 may be completely independent from the circuits of the parent hybrids I and C.

本発明によれば、従来、二次元的な手法によっては、よ
り以上の高密度実装が望み難かったハイブリッドＩＣを
、より高密度化する事がでキモ０従来、ＩＣにとって、
不要な空間であった、ＩＣの上７方に子ハイブリッドＩ
Ｃを多重化して取付けたので、これ−二次元的に見ると
、単位面積あたりの、実装密度は、実効的に高まってい
ることになる。According to the present invention, it is possible to further increase the density of a hybrid IC, which was previously difficult to achieve using two-dimensional methods.
The child hybrid I is placed in the upper part of the IC, which was an unnecessary space.
Since C is mounted in a multiplexed manner, from a two-dimensional perspective, the mounting density per unit area is effectively increased.

実施例では、２つのハイブリッドＩＣを組合わせている
だけであるが、３つのハイブリッドＩＣを組合わして、
多重イビすることもできる。In the example, only two hybrid ICs are combined, but three hybrid ICs are combined,
It is also possible to emit multiple calls.

この場合、親ハイブリッドＩＣの上へ、子ハイブリッド
ＩＣを取りつけ、さらにその上へ孫ハイブリッドＩＣを
取りつける。孫ハイブリッドＩＣ（図示せず）のリード
は、子ハイブリッドＩＣのリード？し穴と、親ハイブリ
ッドＩＣのリード通し穴に挿通されることになる。In this case, the child hybrid IC is mounted on top of the parent hybrid IC, and the grandchild hybrid IC is further mounted on top of it. Are the leads of the grandchild hybrid IC (not shown) the leads of the child hybrid IC? It will be inserted into the lead hole and the lead hole of the parent hybrid IC.

ハイブリッドＩＣは、モノリシックＩＣに比して、縦横
の寸法が、容易に設定することができるから、リードの
間隔も適当に決定することができる。このため、ハイブ
リッドＩＣを、親、子間でリードを共通にして結合する
のは、極めて好都合である。Since the vertical and horizontal dimensions of a hybrid IC can be more easily set than that of a monolithic IC, the lead spacing can also be appropriately determined. For this reason, it is extremely convenient to connect hybrid ICs by using a common lead between the parent and child.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例に係る多重構造ハイブリッドＩ
Ｃの斜視図。 第２図は第１図中の１−Ｉ断面図。 １・・・・・・親ハイブリッドＩＣ ２・・・・・子ハイブリッドＩＣ ３・・・親ハイブリッドＩＣリード ４・・・・・子ハイブリッドＩ’　Ｃリード５．６・・
・・・・ハ　ン　ダ ７・・・・・リード通し穴 ８・・・・・・電極ハターン ９・・・・・結合ハンダ ４ａ・・・・・非結合リード ４ｂ・・・・・結合リード 発　　明　　者　　　　　　　　武　　内　　省　　二
１）　仲　　正　　敏 上　　１）　　　　穣FIG. 1 shows a multi-structure hybrid I according to an embodiment of the present invention.
A perspective view of C. FIG. 2 is a sectional view taken along line 1-I in FIG. 1...Parent hybrid IC 2...Child hybrid IC 3...Parent hybrid IC lead 4...Child hybrid I'C lead 5.6...
... Solder 7 ... Lead through hole 8 ... Electrode pattern 9 ... Bonding solder 4a ... Non-bonding lead 4b ... Bonding lead Inventor: Sho Takeuchi 21) Toshigami Nakamasa 1) Jo

Claims (2)

【特許請求の範囲】[Claims] （１）親ハイブリッドＩＣにリード通し穴を穿っておき
、子ハイブリッドＩＣのリードを親ハイブリッドＩＣの
リード通し穴へ挿通し、子ハイフリットＩＣリードのい
くつかヲ親ハイブリッドＩＣの基板へ固定した事を特徴
とする多重構造ハイブリッドＩＣ。(1) Drill lead through holes in the parent hybrid IC, insert the leads of the child hybrid IC into the lead through holes of the parent hybrid IC, and fix some of the child high frit IC leads to the board of the parent hybrid IC. A multi-structure hybrid IC characterized by: （２）　　親ハイブリッドＩＣと子ハイブリッドＩＣと
に於て、共通するリードは基板上でハンダ付−けし、両
者の内一方を取り除いた特許請求の範１第１項記載の多
重構造ハイブリッドＩ０(2) In the parent hybrid IC and the child hybrid IC, the common leads are soldered on the substrate, and one of the leads is removed.
JP57028480A 1982-02-24 1982-02-24 Multi-structural hybrid integrated circuit Pending JPS58147052A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57028480A JPS58147052A (en) 1982-02-24 1982-02-24 Multi-structural hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57028480A JPS58147052A (en) 1982-02-24 1982-02-24 Multi-structural hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS58147052A true JPS58147052A (en) 1983-09-01

Family

ID=12249813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57028480A Pending JPS58147052A (en) 1982-02-24 1982-02-24 Multi-structural hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS58147052A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5061989A (en) * 1990-03-22 1991-10-29 Transcomputer, Inc. Mechanical translator for semiconductor chips

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5061989A (en) * 1990-03-22 1991-10-29 Transcomputer, Inc. Mechanical translator for semiconductor chips

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