JPS5927061Y2 - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS5927061Y2 JPS5927061Y2 JP1979067927U JP6792779U JPS5927061Y2 JP S5927061 Y2 JPS5927061 Y2 JP S5927061Y2 JP 1979067927 U JP1979067927 U JP 1979067927U JP 6792779 U JP6792779 U JP 6792779U JP S5927061 Y2 JPS5927061 Y2 JP S5927061Y2
- Authority
- JP
- Japan
- Prior art keywords
- hybrid integrated
- integrated circuit
- circuit device
- board
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
- Mounting Of Printed Circuit Boards And The Like (AREA)
Description
【考案の詳細な説明】
本考案は混成集積回路の組立て構造に関し、高密度実装
を計りつつ組立てを容易にし、又各機能回路ブロック毎
に混成集積回路化することに依り、それら回路ブロック
毎の検査を行い、品質管理を容易にし、且つ歩留りの向
上を計ることを目的とする。[Detailed description of the invention] The present invention relates to the assembly structure of a hybrid integrated circuit, which facilitates assembly while ensuring high-density packaging, and by converting each functional circuit block into a hybrid integrated circuit. The purpose is to conduct inspections, facilitate quality control, and improve yield.
第1図は従来の混成集積回路の組立図を示し、基板A、
B、C,D上に電極、抵抗、コンデンサ等の受動素子を
印刷配線し、その後チップコンデンサ、ボリューム等の
部品を半田付けし、多層に重ねてノード端子で各基板の
端子同志の導通を計り、同時に機械的に固定している。FIG. 1 shows an assembly diagram of a conventional hybrid integrated circuit.
Passive elements such as electrodes, resistors, and capacitors are printed and wired on B, C, and D, and then parts such as chip capacitors and volumes are soldered, stacked in multiple layers, and the node terminals are used to measure continuity between the terminals of each board. , and is mechanically fixed at the same time.
多ブロックからなる回路をこの様な方法で混成集積回路
化する場合、各基板毎に独立した回路ブロックを配する
ことがパターンの設計上困難で、例えば基板Aに配すべ
き回路ブロックの1部分又は1部品が基板B又は他の基
板に配される為、一つの機能を持つ回路ブロックが独立
しておらず、各基板毎の検査が非常に困難である。When a circuit consisting of multiple blocks is fabricated into a hybrid integrated circuit using this method, it is difficult to arrange an independent circuit block on each board due to pattern design. Alternatively, since one component is placed on board B or another board, circuit blocks having one function are not independent, making it extremely difficult to inspect each board.
又この様な方法の組立ては困難で長時間を要する。Also, assembly using this method is difficult and time consuming.
何故ならばリード端子を全ての端子孔に挿入するのでは
なく、夫々の個所で限定されている為その作業及び管理
が大変であるからである。This is because the lead terminals are not inserted into all the terminal holes, but are limited to each location, making the work and management difficult.
上述した従来の種々の欠点に鑑み威された本考案の一実
施例について第2図乃至第4図について説明する。An embodiment of the present invention, which has been developed in view of the various drawbacks of the prior art described above, will be described with reference to FIGS. 2 to 4.
第2図は混成集積回路1,2の上下に基板3,4をノー
ド端子りで電気機械的に接続して組立てた正面図を示し
、第3図は第2図の側面図、第4図は第2図の平面図を
夫々示す。FIG. 2 shows a front view of the hybrid integrated circuits 1 and 2, which are assembled by electromechanically connecting substrates 3 and 4 above and below with node terminals, FIG. 3 is a side view of FIG. 2, and FIG. 2 shows the plan view of FIG. 2, respectively.
混成集積回路1,2はシングル・イン・ラインパッケイ
ジ(SIP)型のICで夫々一つの回路ブロックを混成
集積回路化されたもので、これら樹脂でパッケイジされ
ている。The hybrid integrated circuits 1 and 2 are single-in-line package (SIP) type ICs, each of which is formed from one circuit block into a hybrid integrated circuit, and is packaged with these resins.
印刷配線のされている下側基板4に電気機械的に端子5
を半田にて接続取付けし、これらを組立て治具に挿入し
く図示せず)、印刷配線上に半固定抵抗6゜7、ダイオ
ード8,9等の電気部品が取付けられた上側基板を前記
組立て治具に載せて、混成集積回路の周囲にリード端子
を半田付けすることにより上下基板3,4を電気機械的
に接続固定する。Terminals 5 are electromechanically attached to the lower board 4 on which the printed wiring is installed.
(not shown), and the upper board, on which electric components such as a semi-fixed resistor 6.7 and diodes 8 and 9 are attached on the printed wiring, is inserted into the assembly jig (not shown). The upper and lower substrates 3 and 4 are electromechanically connected and fixed by soldering lead terminals around the hybrid integrated circuit.
次にダイオード10、コンデンサ11.抵抗12を上下
基板3.4間に取付は接続する。Next, a diode 10, a capacitor 11. A resistor 12 is mounted and connected between the upper and lower boards 3 and 4.
この様な組立て方を例えば高周波回路に適用して、混成
集積回路1,2間に金属シールド板を介在させれば、回
路ブロック間(段間)のシールドができるという利点が
ある。If such an assembly method is applied to, for example, a high frequency circuit and a metal shield plate is interposed between the hybrid integrated circuits 1 and 2, there is an advantage that shielding between circuit blocks (interstages) can be achieved.
以上述べた様な本考案の構成によれば、回路ブロック毎
の良否の検査を実施した後組立てられるので組立完成後
の歩留りを飛躍的に向上させる事が出来る。According to the configuration of the present invention as described above, since each circuit block is assembled after inspecting its quality, the yield after assembly is completed can be dramatically improved.
又リード端子の取付けに於いては従来の様に取付個所に
限定があったす、リード端子の長さもまちまちであった
為、組立作業が困難で長時間を要していたが、本考案で
はそれらの問題点は一掃され、高密実装を維持しながら
作業の能率を向上させることができるものである。In addition, when attaching lead terminals, as in the past, there were limitations on where to attach them and the lengths of the lead terminals also varied, making assembly work difficult and time-consuming. These problems can be eliminated and work efficiency can be improved while maintaining high density packaging.
第1図は従来例の混成集積回路装置、第2図は本考案の
一実施例の混成集積回路装置の正面図、第3図は第2図
の側面図、第4図は第2図の平面図を示す。
1.2・・・・・・混成集積回路、3・・・・・・上側
基板、4・・・・・・下側基板。1 is a conventional hybrid integrated circuit device, FIG. 2 is a front view of a hybrid integrated circuit device according to an embodiment of the present invention, FIG. 3 is a side view of FIG. 2, and FIG. 4 is a side view of FIG. 2. A plan view is shown. 1.2...Hybrid integrated circuit, 3...Upper board, 4...Lower board.
Claims (1)
板に前記混成集積回路を取付け、前記混成集積回路の周
囲に前記上下基板間をリード端子で電気機械的に接続し
た混成集積回路装置。A hybrid integrated circuit device in which substrates are disposed oppositely above and below a hybrid integrated circuit, the hybrid integrated circuit is attached to the lower substrate, and the upper and lower substrates are electromechanically connected around the hybrid integrated circuit by lead terminals. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1979067927U JPS5927061Y2 (en) | 1979-05-21 | 1979-05-21 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1979067927U JPS5927061Y2 (en) | 1979-05-21 | 1979-05-21 | Hybrid integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55167685U JPS55167685U (en) | 1980-12-02 |
JPS5927061Y2 true JPS5927061Y2 (en) | 1984-08-06 |
Family
ID=29301812
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1979067927U Expired JPS5927061Y2 (en) | 1979-05-21 | 1979-05-21 | Hybrid integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5927061Y2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5127152A (en) * | 1974-08-30 | 1976-03-06 | Teikoku Sanso Kk | NANSAISENJOBUTSUOFUKUNDA HASAIBUTSUNOHASAIHOHO |
-
1979
- 1979-05-21 JP JP1979067927U patent/JPS5927061Y2/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5127152A (en) * | 1974-08-30 | 1976-03-06 | Teikoku Sanso Kk | NANSAISENJOBUTSUOFUKUNDA HASAIBUTSUNOHASAIHOHO |
Also Published As
Publication number | Publication date |
---|---|
JPS55167685U (en) | 1980-12-02 |
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