JPS5814266A - マルチプロセツサ装置の制御方式 - Google Patents

マルチプロセツサ装置の制御方式

Info

Publication number
JPS5814266A
JPS5814266A JP56110859A JP11085981A JPS5814266A JP S5814266 A JPS5814266 A JP S5814266A JP 56110859 A JP56110859 A JP 56110859A JP 11085981 A JP11085981 A JP 11085981A JP S5814266 A JPS5814266 A JP S5814266A
Authority
JP
Japan
Prior art keywords
slave
processor
cpu4
stop
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56110859A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0215094B2 (enrdf_load_stackoverflow
Inventor
Tatsuya Kano
狩野　達弥
Manabu Iwata
学 岩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56110859A priority Critical patent/JPS5814266A/ja
Publication of JPS5814266A publication Critical patent/JPS5814266A/ja
Publication of JPH0215094B2 publication Critical patent/JPH0215094B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP56110859A 1981-07-17 1981-07-17 マルチプロセツサ装置の制御方式 Granted JPS5814266A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56110859A JPS5814266A (ja) 1981-07-17 1981-07-17 マルチプロセツサ装置の制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56110859A JPS5814266A (ja) 1981-07-17 1981-07-17 マルチプロセツサ装置の制御方式

Publications (2)

Publication Number Publication Date
JPS5814266A true JPS5814266A (ja) 1983-01-27
JPH0215094B2 JPH0215094B2 (enrdf_load_stackoverflow) 1990-04-11

Family

ID=14546475

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56110859A Granted JPS5814266A (ja) 1981-07-17 1981-07-17 マルチプロセツサ装置の制御方式

Country Status (1)

Country Link
JP (1) JPS5814266A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04294440A (ja) * 1991-03-22 1992-10-19 Koufu Nippon Denki Kk プロセッサ間データ転送システム

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0666593U (ja) * 1993-03-02 1994-09-20 積水樹脂株式会社 物干しハンガー

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04294440A (ja) * 1991-03-22 1992-10-19 Koufu Nippon Denki Kk プロセッサ間データ転送システム

Also Published As

Publication number Publication date
JPH0215094B2 (enrdf_load_stackoverflow) 1990-04-11

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