JPS58140636U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS58140636U
JPS58140636U JP3659582U JP3659582U JPS58140636U JP S58140636 U JPS58140636 U JP S58140636U JP 3659582 U JP3659582 U JP 3659582U JP 3659582 U JP3659582 U JP 3659582U JP S58140636 U JPS58140636 U JP S58140636U
Authority
JP
Japan
Prior art keywords
semiconductor element
solder material
semiconductor equipment
heat sink
covered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3659582U
Other languages
English (en)
Japanese (ja)
Other versions
JPS6344991Y2 (enrdf_load_stackoverflow
Inventor
明 山岸
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP3659582U priority Critical patent/JPS58140636U/ja
Publication of JPS58140636U publication Critical patent/JPS58140636U/ja
Application granted granted Critical
Publication of JPS6344991Y2 publication Critical patent/JPS6344991Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Wire Bonding (AREA)
JP3659582U 1982-03-16 1982-03-16 半導体装置 Granted JPS58140636U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3659582U JPS58140636U (ja) 1982-03-16 1982-03-16 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3659582U JPS58140636U (ja) 1982-03-16 1982-03-16 半導体装置

Publications (2)

Publication Number Publication Date
JPS58140636U true JPS58140636U (ja) 1983-09-21
JPS6344991Y2 JPS6344991Y2 (enrdf_load_stackoverflow) 1988-11-22

Family

ID=30048019

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3659582U Granted JPS58140636U (ja) 1982-03-16 1982-03-16 半導体装置

Country Status (1)

Country Link
JP (1) JPS58140636U (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS6344991Y2 (enrdf_load_stackoverflow) 1988-11-22

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